1 /*
2 * Copyright 2002 Momentum Computer
3 * Author: mdharm@momenco.com
4 *
5 * arch/mips/momentum/ocelot_c/mv-irq.c
6 * Interrupt routines for mv64340. Interrupt numbers are assigned from
7 * MV64340_IRQ_BASE to MV64340_IRQ_BASE+64.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <asm/ptrace.h>
20 #include <linux/config.h>
21 #include <linux/sched.h>
22 #include <linux/kernel_stat.h>
23 #include <asm/io.h>
24 #include <asm/mv64340.h>
25
26 #define MV64340_IRQ_BASE 16
27
ls1bit32(unsigned int x)28 static inline int ls1bit32(unsigned int x)
29 {
30 int b = 31, s;
31
32 s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s;
33 s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s;
34 s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s;
35 s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s;
36 s = 1; if (x << 1 == 0) s = 0; b -= s;
37
38 return b;
39 }
40
41 /* mask off an interrupt -- 1 is enable, 0 is disable */
mask_mv64340_irq(unsigned int irq)42 static inline void mask_mv64340_irq(unsigned int irq)
43 {
44 uint32_t value;
45
46 if (irq < (MV64340_IRQ_BASE + 32)) {
47 MV_READ(MV64340_INTERRUPT0_MASK_0_LOW, &value);
48 value &= ~(1 << (irq - MV64340_IRQ_BASE));
49 MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value);
50 } else {
51 MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH, &value);
52 value &= ~(1 << (irq - (MV64340_IRQ_BASE - 32)));
53 MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value);
54 }
55 }
56
57 /* unmask an interrupt -- 1 is enable, 0 is disable */
unmask_mv64340_irq(unsigned int irq)58 static inline void unmask_mv64340_irq(unsigned int irq)
59 {
60 uint32_t value;
61
62 if (irq < (MV64340_IRQ_BASE + 32)) {
63 MV_READ(MV64340_INTERRUPT0_MASK_0_LOW, &value);
64 value |= 1 << (irq - MV64340_IRQ_BASE);
65 MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value);
66 } else {
67 MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH, &value);
68 value |= 1 << (irq - (MV64340_IRQ_BASE - 32));
69 MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value);
70 }
71 }
72
73 /*
74 * Enables the IRQ on Marvell Chip
75 */
enable_mv64340_irq(unsigned int irq)76 static void enable_mv64340_irq(unsigned int irq)
77 {
78 unmask_mv64340_irq(irq);
79 }
80
81 /*
82 * Initialize the IRQ on Marvell Chip
83 */
startup_mv64340_irq(unsigned int irq)84 static unsigned int startup_mv64340_irq(unsigned int irq)
85 {
86 unmask_mv64340_irq(irq);
87 return 0;
88 }
89
90 /*
91 * Disables the IRQ on Marvell Chip
92 */
disable_mv64340_irq(unsigned int irq)93 static void disable_mv64340_irq(unsigned int irq)
94 {
95 mask_mv64340_irq(irq);
96 }
97
98 /*
99 * Masks and ACKs an IRQ
100 */
mask_and_ack_mv64340_irq(unsigned int irq)101 static void mask_and_ack_mv64340_irq(unsigned int irq)
102 {
103 mask_mv64340_irq(irq);
104 }
105
106 /*
107 * End IRQ processing
108 */
end_mv64340_irq(unsigned int irq)109 static void end_mv64340_irq(unsigned int irq)
110 {
111 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
112 unmask_mv64340_irq(irq);
113 }
114
115 /*
116 * Interrupt handler for interrupts coming from the Marvell chip.
117 * It could be built in ethernet ports etc...
118 */
ll_mv64340_irq(struct pt_regs * regs)119 void ll_mv64340_irq(struct pt_regs *regs)
120 {
121 unsigned int irq_src_low, irq_src_high;
122 unsigned int irq_mask_low, irq_mask_high;
123
124 /* read the interrupt status registers */
125 MV_READ(MV64340_INTERRUPT0_MASK_0_LOW, &irq_mask_low);
126 MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH, &irq_mask_high);
127 MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_LOW, &irq_src_low);
128 MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_HIGH, &irq_src_high);
129
130 /* mask for just the interrupts we want */
131 irq_src_low &= irq_mask_low;
132 irq_src_high &= irq_mask_high;
133
134 if (irq_src_low)
135 do_IRQ(ls1bit32(irq_src_low) + MV64340_IRQ_BASE, regs);
136 else
137 do_IRQ(ls1bit32(irq_src_high) + MV64340_IRQ_BASE + 32, regs);
138 }
139
140 #define shutdown_mv64340_irq disable_mv64340_irq
141
142 struct hw_interrupt_type mv64340_irq_type = {
143 "MV-64340",
144 startup_mv64340_irq,
145 shutdown_mv64340_irq,
146 enable_mv64340_irq,
147 disable_mv64340_irq,
148 mask_and_ack_mv64340_irq,
149 end_mv64340_irq,
150 NULL
151 };
152
mv64340_irq_init(void)153 void mv64340_irq_init(void)
154 {
155 int i;
156
157 /* Reset irq handlers pointers to NULL */
158 for (i = MV64340_IRQ_BASE; i < (MV64340_IRQ_BASE + 64); i++) {
159 irq_desc[i].status = IRQ_DISABLED;
160 irq_desc[i].action = 0;
161 irq_desc[i].depth = 2;
162 irq_desc[i].handler = &mv64340_irq_type;
163 }
164 }
165