1 /*
2 * Copyright (C) 2000 RidgeRun, Inc.
3 * Author: RidgeRun, Inc.
4 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
8 * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org)
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 *
30 */
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/kernel_stat.h>
34 #include <linux/module.h>
35 #include <linux/signal.h>
36 #include <linux/sched.h>
37 #include <linux/types.h>
38 #include <linux/interrupt.h>
39 #include <linux/ioport.h>
40 #include <linux/timex.h>
41 #include <linux/slab.h>
42 #include <linux/random.h>
43 #include <asm/bitops.h>
44 #include <asm/bootinfo.h>
45 #include <asm/io.h>
46 #include <asm/irq.h>
47 #include <asm/mipsregs.h>
48 #include <asm/system.h>
49
50
51 static spinlock_t irq_lock = SPIN_LOCK_UNLOCKED;
52
53 /* Function for careful CP0 interrupt mask access */
modify_cp0_intmask(unsigned clr_mask_in,unsigned set_mask_in)54 static inline void modify_cp0_intmask(unsigned clr_mask_in, unsigned set_mask_in)
55 {
56 unsigned long status;
57 unsigned clr_mask;
58 unsigned set_mask;
59
60 /* do the low 8 bits first */
61 clr_mask = 0xff & clr_mask_in;
62 set_mask = 0xff & set_mask_in;
63 status = read_c0_status();
64 status &= ~((clr_mask & 0xFF) << 8);
65 status |= (set_mask & 0xFF) << 8;
66 write_c0_status(status);
67 }
68
mask_irq(unsigned int irq)69 static inline void mask_irq(unsigned int irq)
70 {
71 modify_cp0_intmask(irq, 0);
72 }
73
unmask_irq(unsigned int irq)74 static inline void unmask_irq(unsigned int irq)
75 {
76 modify_cp0_intmask(0, irq);
77 }
78
enable_cp7000_irq(unsigned int irq)79 static void enable_cp7000_irq(unsigned int irq)
80 {
81 unsigned long flags;
82
83 spin_lock_irqsave(&irq_lock, flags);
84 unmask_irq(1 << irq);
85 spin_unlock_irqrestore(&irq_lock, flags);
86 }
87
startup_cp7000_irq(unsigned int irq)88 static unsigned int startup_cp7000_irq(unsigned int irq)
89 {
90 enable_cp7000_irq(irq);
91
92 return 0; /* never anything pending */
93 }
94
disable_cp7000_irq(unsigned int irq)95 static void disable_cp7000_irq(unsigned int irq)
96 {
97 unsigned long flags;
98
99 spin_lock_irqsave(&irq_lock, flags);
100 mask_irq(1 << irq);
101 spin_unlock_irqrestore(&irq_lock, flags);
102 }
103
104 #define shutdown_cp7000_irq disable_cp7000_irq
105
mask_and_ack_cp7000_irq(unsigned int irq)106 static void mask_and_ack_cp7000_irq(unsigned int irq)
107 {
108 mask_irq(1 << irq);
109 }
110
end_cp7000_irq(unsigned int irq)111 static void end_cp7000_irq(unsigned int irq)
112 {
113 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
114 unmask_irq(1 << irq);
115 }
116
117 static struct hw_interrupt_type cp7000_hpcdma_irq_type = {
118 #ifdef CONFIG_CPU_SR71000
119 "SR71000",
120 #else
121 "RM7000",
122 #endif
123 startup_cp7000_irq,
124 shutdown_cp7000_irq,
125 enable_cp7000_irq,
126 disable_cp7000_irq,
127 mask_and_ack_cp7000_irq,
128 end_cp7000_irq,
129 NULL
130 };
131
132 extern asmlinkage void ocelot_handle_int(void);
133 extern void mv64340_irq_init(void);
134 extern void uart_irq_init(void);
135 extern void cpci_irq_init(void);
136
137 static struct irqaction cascade_fpga =
138 { no_action, SA_INTERRUPT, 0, "cascade via FPGA", NULL, NULL };
139 static struct irqaction cascade_mv64340 =
140 { no_action, SA_INTERRUPT, 0, "cascade via MV64340", NULL, NULL };
141
init_IRQ(void)142 void __init init_IRQ(void)
143 {
144 int i;
145
146 /*
147 * Clear all of the interrupts while we change the able around a bit.
148 * int-handler is not on bootstrap
149 */
150 clear_c0_status(ST0_IM | ST0_BEV);
151 __cli();
152
153 /* Sets the first-level interrupt dispatcher. */
154 set_except_vector(0, ocelot_handle_int);
155 init_generic_irq();
156
157 /* set up handler for first 8 IRQs as the CPU */
158 for (i = 0; i < 8; i++) {
159 irq_desc[i].status = IRQ_DISABLED;
160 irq_desc[i].action = 0;
161 irq_desc[i].depth = 1;
162 irq_desc[i].handler = &cp7000_hpcdma_irq_type;
163 }
164
165 /* set up the cascading interrupts */
166 setup_irq(3, &cascade_fpga);
167 setup_irq(5, &cascade_fpga);
168 setup_irq(6, &cascade_mv64340);
169
170 mv64340_irq_init();
171 uart_irq_init();
172 cpci_irq_init();
173
174 #ifdef CONFIG_KGDB
175 printk("start kgdb ...\n");
176 set_debug_traps();
177 breakpoint(); /* you may move this line to whereever you want :-) */
178 #endif
179 #ifdef CONFIG_GDB_CONSOLE
180 register_gdb_console();
181 #endif
182 }
183