1 /*
2 * Copyright 2002 Momentum Computer
3 * Author: mdharm@momenco.com
4 *
5 * arch/mips/momentum/ocelot_c/cpci-irq.c
6 * Interrupt routines for cpci. Interrupt numbers are assigned from
7 * CPCI_IRQ_BASE to CPCI_IRQ_BASE+8 (8 interrupt sources).
8 *
9 * Note that the high-level software will need to be careful about using
10 * these interrupts. If this board is asserting a cPCI interrupt, it will
11 * also see the asserted interrupt. Care must be taken to avoid an
12 * interrupt flood.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 */
19
20 #include <linux/module.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/kernel.h>
24 #include <asm/ptrace.h>
25 #include <linux/config.h>
26 #include <linux/sched.h>
27 #include <linux/kernel_stat.h>
28 #include <asm/io.h>
29 #include "ocelot_c_fpga.h"
30
31 #define CPCI_IRQ_BASE 8
32
ls1bit8(unsigned int x)33 static inline int ls1bit8(unsigned int x)
34 {
35 int b = 7, s;
36
37 s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s;
38 s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s;
39 s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s;
40
41 return b;
42 }
43
44 /* mask off an interrupt -- 0 is enable, 1 is disable */
mask_cpci_irq(unsigned int irq)45 static inline void mask_cpci_irq(unsigned int irq)
46 {
47 uint32_t value;
48
49 value = OCELOT_FPGA_READ(INTMASK);
50 value |= 1 << (irq - CPCI_IRQ_BASE);
51 OCELOT_FPGA_WRITE(value, INTMASK);
52
53 /* read the value back to assure that it's really been written */
54 value = OCELOT_FPGA_READ(INTMASK);
55 }
56
57 /* unmask an interrupt -- 0 is enable, 1 is disable */
unmask_cpci_irq(unsigned int irq)58 static inline void unmask_cpci_irq(unsigned int irq)
59 {
60 uint32_t value;
61
62 value = OCELOT_FPGA_READ(INTMASK);
63 value &= ~(1 << (irq - CPCI_IRQ_BASE));
64 OCELOT_FPGA_WRITE(value, INTMASK);
65
66 /* read the value back to assure that it's really been written */
67 value = OCELOT_FPGA_READ(INTMASK);
68 }
69
70 /*
71 * Enables the IRQ in the FPGA
72 */
enable_cpci_irq(unsigned int irq)73 static void enable_cpci_irq(unsigned int irq)
74 {
75 unmask_cpci_irq(irq);
76 }
77
78 /*
79 * Initialize the IRQ in the FPGA
80 */
startup_cpci_irq(unsigned int irq)81 static unsigned int startup_cpci_irq(unsigned int irq)
82 {
83 unmask_cpci_irq(irq);
84 return 0;
85 }
86
87 /*
88 * Disables the IRQ in the FPGA
89 */
disable_cpci_irq(unsigned int irq)90 static void disable_cpci_irq(unsigned int irq)
91 {
92 mask_cpci_irq(irq);
93 }
94
95 /*
96 * Masks and ACKs an IRQ
97 */
mask_and_ack_cpci_irq(unsigned int irq)98 static void mask_and_ack_cpci_irq(unsigned int irq)
99 {
100 mask_cpci_irq(irq);
101 }
102
103 /*
104 * End IRQ processing
105 */
end_cpci_irq(unsigned int irq)106 static void end_cpci_irq(unsigned int irq)
107 {
108 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
109 unmask_cpci_irq(irq);
110 }
111
112 /*
113 * Interrupt handler for interrupts coming from the FPGA chip.
114 * It could be built in ethernet ports etc...
115 */
ll_cpci_irq(struct pt_regs * regs)116 void ll_cpci_irq(struct pt_regs *regs)
117 {
118 unsigned int irq_src, irq_mask;
119
120 /* read the interrupt status registers */
121 irq_src = OCELOT_FPGA_READ(INTSTAT);
122 irq_mask = OCELOT_FPGA_READ(INTMASK);
123
124 /* mask for just the interrupts we want */
125 irq_src &= ~irq_mask;
126
127 do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE, regs);
128 }
129
130 #define shutdown_cpci_irq disable_cpci_irq
131
132 struct hw_interrupt_type cpci_irq_type = {
133 "CPCI/FPGA",
134 startup_cpci_irq,
135 shutdown_cpci_irq,
136 enable_cpci_irq,
137 disable_cpci_irq,
138 mask_and_ack_cpci_irq,
139 end_cpci_irq,
140 NULL
141 };
142
cpci_irq_init(void)143 void cpci_irq_init(void)
144 {
145 int i;
146
147 /* Reset irq handlers pointers to NULL */
148 for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++) {
149 irq_desc[i].status = IRQ_DISABLED;
150 irq_desc[i].action = 0;
151 irq_desc[i].depth = 2;
152 irq_desc[i].handler = &cpci_irq_type;
153 }
154 }
155