1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License.  See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995 Waldorf Electronics
7 * Written by Ralf Baechle and Andreas Busse
8 * Copyright (C) 1995 - 1999 Ralf Baechle
9 * Copyright (C) 1996 Paul M. Antoine
10 * Modified for DECStation and hence R3000 support by Paul M. Antoine
11 * Further modifications by David S. Miller and Harald Koerfgen
12 * Copyright (C) 1999 Silicon Graphics, Inc.
13 *
14 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
15 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
16 */
17#include <linux/config.h>
18#include <linux/init.h>
19#include <linux/threads.h>
20
21#include <asm/asm.h>
22#include <asm/current.h>
23#include <asm/offset.h>
24#include <asm/pgtable-bits.h>
25#include <asm/processor.h>
26#include <asm/regdef.h>
27#include <asm/cachectl.h>
28#include <asm/mipsregs.h>
29#include <asm/stackframe.h>
30
31		.text
32		/*
33		 * Reserved space for exception handlers.
34		 * Necessary for machines which link their kernels at KSEG0.
35		 */
36		.fill	0x400
37
38		/* The following two symbols are used for kernel profiling. */
39		EXPORT(stext)
40		EXPORT(_stext)
41
42		__INIT
43
44		/* Cache Error */
45		LEAF(except_vec2_generic)
46		.set	noreorder
47		.set	noat
48		.set    mips0
49		/*
50		 * This is a very bad place to be.  Our cache error
51		 * detection has triggered.  If we have write-back data
52		 * in the cache, we may not be able to recover.  As a
53		 * first-order desperate measure, turn off KSEG0 cacheing.
54		 */
55		mfc0	k0,CP0_CONFIG
56		li	k1,~CONF_CM_CMASK
57		and	k0,k0,k1
58		ori	k0,k0,CONF_CM_UNCACHED
59		mtc0	k0,CP0_CONFIG
60		/* Give it a few cycles to sink in... */
61		nop
62		nop
63		nop
64
65		j	cache_parity_error
66		 nop
67		END(except_vec2_generic)
68
69		.set	at
70
71		/*
72		 * Special interrupt vector for embedded MIPS.  This is a
73		 * dedicated interrupt vector which reduces interrupt processing
74		 * overhead.  The jump instruction will be inserted here at
75		 * initialization time.  This handler may only be 8 bytes in
76		 * size!
77		 */
78		NESTED(except_vec4, 0, sp)
791:		j	1b			/* Dummy, will be replaced */
80		 nop
81		END(except_vec4)
82
83		/*
84		 * EJTAG debug exception handler.
85		 * The EJTAG debug exception entry point is 0xbfc00480, which
86		 * normally is in the boot PROM, so the boot PROM must do a
87		 * unconditional jump to this vector.
88		 */
89		NESTED(except_vec_ejtag_debug, 0, sp)
90		j	ejtag_debug_handler
91		 nop
92		END(except_vec_ejtag_debug)
93
94		__FINIT
95
96		/*
97		 * EJTAG debug exception handler.
98		 */
99		NESTED(ejtag_debug_handler, PT_SIZE, sp)
100		.set	noat
101		.set	noreorder
102		mtc0	k0, CP0_DESAVE
103		mfc0	k0, CP0_DEBUG
104
105		sll	k0, k0, 30	# Check for SDBBP.
106		bgez	k0, ejtag_return
107
108		 la	k0, ejtag_debug_buffer
109		sw	k1, 0(k0)
110		SAVE_ALL
111		jal	ejtag_exception_handler
112		 move	a0, sp
113		RESTORE_ALL
114		la	k0, ejtag_debug_buffer
115		lw	k1, 0(k0)
116
117ejtag_return:
118		mfc0	k0, CP0_DESAVE
119		.set	mips32
120		deret
121		.set	mips0
122		 nop
123		.set	at
124		END(ejtag_debug_handler)
125
126		__INIT
127
128		/*
129		* NMI debug exception handler for MIPS reference boards.
130		* The NMI debug exception entry point is 0xbfc00000, which
131		* normally is in the boot PROM, so the boot PROM must do a
132		* unconditional jump to this vector.
133		*/
134		NESTED(except_vec_nmi, 0, sp)
135		j       nmi_handler
136		 nop
137		END(except_vec_nmi)
138
139		__FINIT
140
141		NESTED(nmi_handler, PT_SIZE, sp)
142		.set    noat
143		.set    noreorder
144		.set    mips3
145		SAVE_ALL
146		jal     nmi_exception_handler
147		 move   a0, sp
148		RESTORE_ALL
149		eret
150		.set    at
151		.set    mips0
152		END(nmi_handler)
153
154		__INIT
155
156		/*
157		 * Kernel entry point
158		 */
159		NESTED(kernel_entry, 16, sp)
160		.set	noreorder
161
162		/*
163		 * The firmware/bootloader passes argc/argp/envp
164		 * to us as arguments.  But clear bss first because
165		 * the romvec and other important info is stored there
166		 * by prom_init().
167		 */
168		la	t0, _edata
169		sw	zero, (t0)
170		la	t1, (_end - 4)
1711:
172		addiu	t0, 4
173		bne	t0, t1, 1b
174		 sw	zero, (t0)
175
176		/*
177		 * Stack for kernel and init, current variable
178		 */
179		la	$28, init_task_union
180		addiu	t0, $28, KERNEL_STACK_SIZE-32
181		subu	sp, t0, 4*SZREG
182		sw	t0, kernelsp
183
184		jal	init_arch
185		 nop
186		END(kernel_entry)
187
188
189#ifdef CONFIG_SMP
190
191/*
192 * SMP slave cpus entry point.  Board specific code for bootstrap calls this
193 * function after setting up the stack and gp registers.
194 */
195		LEAF(smp_bootstrap)
196		.set push
197		.set noreorder
198		mtc0	zero, CP0_WIRED
199		CLI
200		mfc0	t0, CP0_STATUS
201		li	t1, ~(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX|ST0_UX)
202		and	t0, t1
203		or	t0, (ST0_CU0);
204		jal	start_secondary
205		 mtc0	t0, CP0_STATUS
206		.set pop
207		END(smp_bootstrap)
208#endif
209
210		__FINIT
211
212		/*
213		 * This buffer is reserved for the use of the EJTAG debug
214		 * handler.
215		 */
216		.data
217		EXPORT(ejtag_debug_buffer)
218		.fill	4
219
220		.comm	kernelsp,    NR_CPUS * 8, 8
221		.comm	pgd_current, NR_CPUS * 8, 8
222
223	.macro	page name, order=0
224	.globl	\name
225\name:	.size	\name, (_PAGE_SIZE << \order)
226	.org	. + (_PAGE_SIZE << \order)
227	.type	\name, @object
228	.endm
229
230	.data
231	.align	12
232
233	page	swapper_pg_dir, _PGD_ORDER
234	page	empty_bad_page, 0
235	page	empty_bad_page_table, 0
236	page	invalid_pte_table, 0
237