1 #include <linux/init.h>
2 #include <linux/kernel.h>
3 #include <linux/stddef.h>
4 #include <asm/bugs.h>
5 #include <asm/cpu.h>
6 #include <asm/fpu.h>
7 #include <asm/mipsregs.h>
8 
9 /*
10  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
11  * the implementation of the "wait" feature differs between CPU families. This
12  * points to the function that implements CPU specific wait.
13  * The wait instruction stops the pipeline and reduces the power consumption of
14  * the CPU very much.
15  */
16 void (*cpu_wait)(void) = NULL;
17 
r3081_wait(void)18 static void r3081_wait(void)
19 {
20 	unsigned long cfg = read_c0_conf();
21 	write_c0_conf(cfg | R30XX_CONF_HALT);
22 }
23 
r39xx_wait(void)24 static void r39xx_wait(void)
25 {
26 	unsigned long cfg = read_c0_conf();
27 	write_c0_conf(cfg | TX39_CONF_HALT);
28 }
29 
r4k_wait(void)30 static void r4k_wait(void)
31 {
32 	__asm__(".set\tmips3\n\t"
33 		"wait\n\t"
34 		".set\tmips0");
35 }
36 
37 /* The Au1xxx wait is available only if we run CONFIG_PM and
38  * the timer setup found we had a 32KHz counter available.
39  * There are still problems with functions that may call au1k_wait
40  * directly, but that will be discovered pretty quickly.
41  */
42 extern void (*au1k_wait_ptr)(void);
au1k_wait(void)43 void au1k_wait(void)
44 {
45 #ifdef CONFIG_PM
46 	unsigned long addr;
47 	/* using the wait instruction makes CP0 counter unusable */
48 	__asm__("la %0,au1k_wait\n\t"
49 		".set mips3\n\t"
50 		"cache 0x14,0(%0)\n\t"
51 		"cache 0x14,32(%0)\n\t"
52 		"sync\n\t"
53 		"nop\n\t"
54 		"wait\n\t"
55 		"nop\n\t"
56 		"nop\n\t"
57 		"nop\n\t"
58 		"nop\n\t"
59 		".set mips0\n\t"
60 		: : "r" (addr));
61 #else
62 	__asm__("nop\n\t"
63 		"nop");
64 #endif
65 }
66 
check_wait(void)67 static inline void check_wait(void)
68 {
69 	struct cpuinfo_mips *c = &current_cpu_data;
70 
71 	printk("Checking for 'wait' instruction... ");
72 	switch (c->cputype) {
73 	case CPU_R3081:
74 	case CPU_R3081E:
75 		cpu_wait = r3081_wait;
76 		printk(" available.\n");
77 		break;
78 	case CPU_TX3927:
79 		cpu_wait = r39xx_wait;
80 		printk(" available.\n");
81 		break;
82 	case CPU_R4200:
83 /*	case CPU_R4300: */
84 	case CPU_R4600:
85 	case CPU_R4640:
86 	case CPU_R4650:
87 	case CPU_R4700:
88 	case CPU_R5000:
89 	case CPU_NEVADA:
90 	case CPU_RM7000:
91 	case CPU_RM9000:
92 	case CPU_TX49XX:
93 	case CPU_4KC:
94 	case CPU_4KEC:
95 	case CPU_4KSC:
96 	case CPU_5KC:
97 /*	case CPU_20KC:*/
98 	case CPU_24K:
99 	case CPU_25KF:
100 		cpu_wait = r4k_wait;
101 		printk(" available.\n");
102 		break;
103 #ifdef CONFIG_PM
104 	case CPU_AU1000:
105 	case CPU_AU1100:
106 	case CPU_AU1500:
107 	case CPU_AU1550:
108 		if (au1k_wait_ptr != NULL) {
109 			cpu_wait = au1k_wait_ptr;
110 			printk(" available.\n");
111 		}
112 		else {
113 			printk(" unavailable.\n");
114 		}
115 		break;
116 #endif
117 	default:
118 		printk(" unavailable.\n");
119 		break;
120 	}
121 }
122 
check_bugs(void)123 void __init check_bugs(void)
124 {
125 	check_wait();
126 }
127 
128 /*
129  * Probe whether cpu has config register by trying to play with
130  * alternate cache bit and see whether it matters.
131  * It's used by cpu_probe to distinguish between R3000A and R3081.
132  */
cpu_has_confreg(void)133 static inline int cpu_has_confreg(void)
134 {
135 #ifdef CONFIG_CPU_R3000
136 	extern unsigned long r3k_cache_size(unsigned long);
137 	unsigned long size1, size2;
138 	unsigned long cfg = read_c0_conf();
139 
140 	size1 = r3k_cache_size(ST0_ISC);
141 	write_c0_conf(cfg ^ R30XX_CONF_AC);
142 	size2 = r3k_cache_size(ST0_ISC);
143 	write_c0_conf(cfg);
144 	return size1 != size2;
145 #else
146 	return 0;
147 #endif
148 }
149 
150 /*
151  * Get the FPU Implementation/Revision.
152  */
cpu_get_fpu_id(void)153 static inline unsigned long cpu_get_fpu_id(void)
154 {
155 	unsigned long tmp, fpu_id;
156 
157 	tmp = read_c0_status();
158 	__enable_fpu();
159 	fpu_id = read_32bit_cp1_register(CP1_REVISION);
160 	write_c0_status(tmp);
161 	return fpu_id;
162 }
163 
164 /*
165  * Check the CPU has an FPU the official way.
166  */
__cpu_has_fpu(void)167 static inline int __cpu_has_fpu(void)
168 {
169 	return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
170 }
171 
172 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
173 		| MIPS_CPU_COUNTER)
174 
cpu_probe_legacy(struct cpuinfo_mips * c)175 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
176 {
177 	switch (c->processor_id & 0xff00) {
178 	case PRID_IMP_R2000:
179 		c->cputype = CPU_R2000;
180 		c->isa_level = MIPS_CPU_ISA_I;
181 		c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
182 		if (__cpu_has_fpu())
183 			c->options |= MIPS_CPU_FPU;
184 		c->tlbsize = 64;
185 		break;
186 	case PRID_IMP_R3000:
187 		if ((c->processor_id & 0xff) == PRID_REV_R3000A)
188 			if (cpu_has_confreg())
189 				c->cputype = CPU_R3081E;
190 			else
191 				c->cputype = CPU_R3000A;
192 		else
193 			c->cputype = CPU_R3000;
194 		c->isa_level = MIPS_CPU_ISA_I;
195 		c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
196 		if (__cpu_has_fpu())
197 			c->options |= MIPS_CPU_FPU;
198 		c->tlbsize = 64;
199 		break;
200 	case PRID_IMP_R4000:
201 		if (read_c0_config() & CONF_SC) {
202 			if ((c->processor_id & 0xff) >= PRID_REV_R4400)
203 				c->cputype = CPU_R4400PC;
204 			else
205 				c->cputype = CPU_R4000PC;
206 		} else {
207 			if ((c->processor_id & 0xff) >= PRID_REV_R4400)
208 				c->cputype = CPU_R4400SC;
209 			else
210 				c->cputype = CPU_R4000SC;
211 		}
212 
213 		c->isa_level = MIPS_CPU_ISA_III;
214 		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
215 		             MIPS_CPU_WATCH | MIPS_CPU_VCE |
216 		             MIPS_CPU_LLSC;
217 		c->tlbsize = 48;
218 		break;
219 	case PRID_IMP_VR41XX:
220 		switch (c->processor_id & 0xf0) {
221 #ifndef CONFIG_VR4181
222 		case PRID_REV_VR4111:
223 			c->cputype = CPU_VR4111;
224 			break;
225 #else
226 		case PRID_REV_VR4181:
227 			c->cputype = CPU_VR4181;
228 			break;
229 #endif
230 		case PRID_REV_VR4121:
231 			c->cputype = CPU_VR4121;
232 			break;
233 		case PRID_REV_VR4122:
234 			if ((c->processor_id & 0xf) < 0x3)
235 				c->cputype = CPU_VR4122;
236 			else
237 				c->cputype = CPU_VR4181A;
238 			break;
239 		case PRID_REV_VR4130:
240 			if ((c->processor_id & 0xf) < 0x4)
241 				c->cputype = CPU_VR4131;
242 			else
243 				c->cputype = CPU_VR4133;
244 			break;
245 		default:
246 			printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
247 				c->cputype = CPU_VR41XX;
248 				break;
249 		}
250 		c->isa_level = MIPS_CPU_ISA_III;
251 		c->options = R4K_OPTS;
252 		c->tlbsize = 32;
253 		break;
254 	case PRID_IMP_R4300:
255 		c->cputype = CPU_R4300;
256 		c->isa_level = MIPS_CPU_ISA_III;
257 		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
258 		             MIPS_CPU_LLSC;
259 		c->tlbsize = 32;
260 		break;
261 	case PRID_IMP_R4600:
262 		c->cputype = CPU_R4600;
263 		c->isa_level = MIPS_CPU_ISA_III;
264 		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
265 		c->tlbsize = 48;
266 		break;
267 	#if 0
268  	case PRID_IMP_R4650:
269 		/*
270 		 * This processor doesn't have an MMU, so it's not
271 		 * "real easy" to run Linux on it. It is left purely
272 		 * for documentation.  Commented out because it shares
273 		 * it's c0_prid id number with the TX3900.
274 		 */
275  		c->cputype = CPU_R4650;
276 	 	c->isa_level = MIPS_CPU_ISA_III;
277 		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
278 	        c->tlbsize = 48;
279 		break;
280 	#endif
281 	case PRID_IMP_TX39:
282 		c->isa_level = MIPS_CPU_ISA_I;
283 		c->options = MIPS_CPU_TLB;
284 
285 		if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
286 			c->cputype = CPU_TX3927;
287 			c->tlbsize = 64;
288 		} else {
289 			switch (c->processor_id & 0xff) {
290 			case PRID_REV_TX3912:
291 				c->cputype = CPU_TX3912;
292 				c->tlbsize = 32;
293 				break;
294 			case PRID_REV_TX3922:
295 				c->cputype = CPU_TX3922;
296 				c->tlbsize = 64;
297 				break;
298 			default:
299 				c->cputype = CPU_UNKNOWN;
300 				break;
301 			}
302 		}
303 		break;
304 	case PRID_IMP_R4700:
305 		c->cputype = CPU_R4700;
306 		c->isa_level = MIPS_CPU_ISA_III;
307 		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
308 		             MIPS_CPU_LLSC;
309 		c->tlbsize = 48;
310 		break;
311 	case PRID_IMP_TX49:
312 		c->cputype = CPU_TX49XX;
313 		c->isa_level = MIPS_CPU_ISA_III;
314 		c->options = R4K_OPTS | MIPS_CPU_LLSC;
315 		if (!(c->processor_id & 0x08))
316 			c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
317 		c->tlbsize = 48;
318 		break;
319 	case PRID_IMP_R5000:
320 		c->cputype = CPU_R5000;
321 		c->isa_level = MIPS_CPU_ISA_IV;
322 		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
323 		             MIPS_CPU_LLSC;
324 		c->tlbsize = 48;
325 		break;
326 	case PRID_IMP_R5432:
327 		c->cputype = CPU_R5432;
328 		c->isa_level = MIPS_CPU_ISA_IV;
329 		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
330 		             MIPS_CPU_WATCH | MIPS_CPU_LLSC;
331 		c->tlbsize = 48;
332 		break;
333 	case PRID_IMP_R5500:
334 		c->cputype = CPU_R5500;
335 		c->isa_level = MIPS_CPU_ISA_IV;
336 		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
337 		             MIPS_CPU_WATCH | MIPS_CPU_LLSC;
338 		c->tlbsize = 48;
339 		break;
340 	case PRID_IMP_NEVADA:
341 		c->cputype = CPU_NEVADA;
342 		c->isa_level = MIPS_CPU_ISA_IV;
343 		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
344 		             MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
345 		c->tlbsize = 48;
346 		break;
347 	case PRID_IMP_R6000:
348 		c->cputype = CPU_R6000;
349 		c->isa_level = MIPS_CPU_ISA_II;
350 		c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
351 		             MIPS_CPU_LLSC;
352 		c->tlbsize = 32;
353 		break;
354 	case PRID_IMP_R6000A:
355 		c->cputype = CPU_R6000A;
356 		c->isa_level = MIPS_CPU_ISA_II;
357 		c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
358 		             MIPS_CPU_LLSC;
359 		c->tlbsize = 32;
360 		break;
361 	case PRID_IMP_RM7000:
362 		c->cputype = CPU_RM7000;
363 		c->isa_level = MIPS_CPU_ISA_IV;
364 		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
365 		             MIPS_CPU_LLSC;
366 		/*
367 		 * Undocumented RM7000:  Bit 29 in the info register of
368 		 * the RM7000 v2.0 indicates if the TLB has 48 or 64
369 		 * entries.
370 		 *
371 		 * 29      1 =>    64 entry JTLB
372 		 *         0 =>    48 entry JTLB
373 		 */
374 		c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
375 		break;
376 	case PRID_IMP_RM9000:
377 		c->cputype = CPU_RM9000;
378 		c->isa_level = MIPS_CPU_ISA_IV;
379 		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
380 			     MIPS_CPU_LLSC;
381 		/*
382 		 * Bit 29 in the info register of the RM9000
383 		 * indicates if the TLB has 48 or 64 entries.
384 		 *
385 		 * 29      1 =>    64 entry JTLB
386 		 *         0 =>    48 entry JTLB
387 		 */
388 		c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
389 		break;
390 	case PRID_IMP_R8000:
391 		c->cputype = CPU_R8000;
392 		c->isa_level = MIPS_CPU_ISA_IV;
393 		c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
394 		             MIPS_CPU_FPU | MIPS_CPU_32FPR |
395 		             MIPS_CPU_LLSC;
396 		c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
397 		break;
398 	case PRID_IMP_R10000:
399 		c->cputype = CPU_R10000;
400 		c->isa_level = MIPS_CPU_ISA_IV;
401 		c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
402 		             MIPS_CPU_FPU | MIPS_CPU_32FPR |
403 			     MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
404 		             MIPS_CPU_LLSC;
405 		c->tlbsize = 64;
406 		break;
407 	case PRID_IMP_R12000:
408 		c->cputype = CPU_R12000;
409 		c->isa_level = MIPS_CPU_ISA_IV;
410 		c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
411 		             MIPS_CPU_FPU | MIPS_CPU_32FPR |
412 			     MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
413 		             MIPS_CPU_LLSC;
414 		c->tlbsize = 64;
415 		break;
416 	default:
417 		c->cputype = CPU_UNKNOWN;
418 		break;
419 	}
420 }
421 
decode_config1(struct cpuinfo_mips * c)422 static inline void decode_config1(struct cpuinfo_mips *c)
423 {
424 	unsigned long config0 = read_c0_config();
425 	unsigned long config1;
426 
427 	if ((config0 & (1 << 31)) == 0)
428 		return;			/* actually wort a panic() */
429 
430 	/* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */
431 	c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
432 		MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
433 		MIPS_CPU_LLSC;
434 	config1 = read_c0_config1();
435 	if (config1 & (1 << 3))
436 		c->options |= MIPS_CPU_WATCH;
437 	if (config1 & (1 << 2))
438 		c->options |= MIPS_CPU_MIPS16;
439 	if (config1 & (1 << 1))
440 		c->options |= MIPS_CPU_EJTAG;
441 	if (config1 & 1) {
442 		c->options |= MIPS_CPU_FPU;
443 		c->options |= MIPS_CPU_32FPR;
444 	}
445 	c->scache.flags = MIPS_CACHE_NOT_PRESENT;
446 
447 	c->tlbsize = ((config1 >> 25) & 0x3f) + 1;
448 }
449 
cpu_probe_mips(struct cpuinfo_mips * c)450 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
451 {
452 	decode_config1(c);
453 	switch (c->processor_id & 0xff00) {
454 	case PRID_IMP_4KC:
455 		c->cputype = CPU_4KC;
456 		c->isa_level = MIPS_CPU_ISA_M32;
457 		break;
458 	case PRID_IMP_4KEC:
459 		c->cputype = CPU_4KEC;
460 		c->isa_level = MIPS_CPU_ISA_M32;
461 		break;
462 	case PRID_IMP_4KSC:
463 		c->cputype = CPU_4KSC;
464 		c->isa_level = MIPS_CPU_ISA_M32;
465 		break;
466 	case PRID_IMP_5KC:
467 		c->cputype = CPU_5KC;
468 		c->isa_level = MIPS_CPU_ISA_M64;
469 		break;
470 	case PRID_IMP_20KC:
471 		c->cputype = CPU_20KC;
472 		c->isa_level = MIPS_CPU_ISA_M64;
473 		break;
474 	case PRID_IMP_24K:
475 		c->cputype = CPU_24K;
476 		c->isa_level = MIPS_CPU_ISA_M32;
477 		break;
478 	case PRID_IMP_25KF:
479 		c->cputype = CPU_25KF;
480 		c->isa_level = MIPS_CPU_ISA_M64;
481 		/* Probe for L2 cache */
482 		c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
483 		break;
484 	default:
485 		c->cputype = CPU_UNKNOWN;
486 		break;
487 	}
488 }
489 
cpu_probe_alchemy(struct cpuinfo_mips * c)490 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
491 {
492 	decode_config1(c);
493 	c->options |= MIPS_CPU_PREFETCH;
494 	switch (c->processor_id & 0xff00) {
495 	case PRID_IMP_AU1_REV1:
496 	case PRID_IMP_AU1_REV2:
497 		switch ((c->processor_id >> 24) & 0xff) {
498 		case 0:
499  			c->cputype = CPU_AU1000;
500 			break;
501 		case 1:
502 			c->cputype = CPU_AU1500;
503 			break;
504 		case 2:
505 			c->cputype = CPU_AU1100;
506 			break;
507 		case 3:
508 			c->cputype = CPU_AU1550;
509 			break;
510 		case 4:
511 			c->cputype = CPU_AU1200;
512 			break;
513 		default:
514 			panic("Unknown Au Core!");
515 			break;
516 		}
517 		c->isa_level = MIPS_CPU_ISA_M32;
518  		break;
519 	default:
520 		c->cputype = CPU_UNKNOWN;
521 		break;
522 	}
523 }
524 
cpu_probe_sibyte(struct cpuinfo_mips * c)525 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
526 {
527 	decode_config1(c);
528 	switch (c->processor_id & 0xff00) {
529 	case PRID_IMP_SB1:
530 		c->cputype = CPU_SB1;
531 		c->isa_level = MIPS_CPU_ISA_M64;
532 		c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
533 		             MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
534 		             MIPS_CPU_MCHECK | MIPS_CPU_EJTAG |
535 		             MIPS_CPU_WATCH | MIPS_CPU_LLSC;
536 #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
537 		/* FPU in pass1 is known to have issues. */
538 		c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
539 #endif
540 		break;
541 	default:
542 		c->cputype = CPU_UNKNOWN;
543 		break;
544 	}
545 }
546 
cpu_probe_sandcraft(struct cpuinfo_mips * c)547 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
548 {
549 	decode_config1(c);
550 	switch (c->processor_id & 0xff00) {
551 	case PRID_IMP_SR71000:
552 		c->cputype = CPU_SR71000;
553 		c->isa_level = MIPS_CPU_ISA_M64;
554 		c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
555                                     MIPS_CPU_4KTLB | MIPS_CPU_FPU |
556 		             MIPS_CPU_COUNTER | MIPS_CPU_MCHECK;
557 		c->scache.ways = 8;
558 		c->tlbsize = 64;
559 		break;
560 	default:
561 		c->cputype = CPU_UNKNOWN;
562 		break;
563 	}
564 }
565 
cpu_probe(void)566 __init void cpu_probe(void)
567 {
568 	struct cpuinfo_mips *c = &current_cpu_data;
569 
570 	c->processor_id	= PRID_IMP_UNKNOWN;
571 	c->fpu_id	= FPIR_IMP_NONE;
572 	c->cputype	= CPU_UNKNOWN;
573 
574 	c->processor_id = read_c0_prid();
575 	switch (c->processor_id & 0xff0000) {
576 
577 	case PRID_COMP_LEGACY:
578 		cpu_probe_legacy(c);
579 		break;
580 	case PRID_COMP_MIPS:
581 		cpu_probe_mips(c);
582 		break;
583 	case PRID_COMP_ALCHEMY:
584 		cpu_probe_alchemy(c);
585 		break;
586 	case PRID_COMP_SIBYTE:
587 		cpu_probe_sibyte(c);
588 		break;
589 
590 	case PRID_COMP_SANDCRAFT:
591 		cpu_probe_sandcraft(c);
592 		break;
593 	default:
594 		c->cputype = CPU_UNKNOWN;
595 	}
596 	if (c->options & MIPS_CPU_FPU)
597 		c->fpu_id = cpu_get_fpu_id();
598 }
599 
cpu_report(void)600 __init void cpu_report(void)
601 {
602 	struct cpuinfo_mips *c = &current_cpu_data;
603 
604 	printk("CPU revision is: %08x\n", c->processor_id);
605 	if (c->options & MIPS_CPU_FPU)
606 		printk("FPU revision is: %08x\n", c->fpu_id);
607 }
608