1 /*
2 * arch/mips/ddb5074/irq.c -- NEC DDB Vrc-5074 interrupt routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7 #include <linux/config.h>
8 #include <linux/init.h>
9 #include <linux/irq.h>
10 #include <linux/signal.h>
11 #include <linux/sched.h>
12 #include <linux/types.h>
13 #include <linux/interrupt.h>
14 #include <linux/ioport.h>
15
16 #include <asm/i8259.h>
17 #include <asm/io.h>
18 #include <asm/irq_cpu.h>
19 #include <asm/ptrace.h>
20 #include <asm/nile4.h>
21 #include <asm/ddb5xxx/ddb5xxx.h>
22 #include <asm/ddb5xxx/ddb5074.h>
23
24
25 extern asmlinkage void ddbIRQ(void);
26
27 static struct irqaction irq_cascade = { no_action, 0, 0, "cascade", NULL, NULL };
28
29 #define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */
30 #define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */
31 #define M1543_PNP_DATA 0x03f1 /* PnP Data Port */
32
33 #define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */
34 #define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */
35 #define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */
36
37 #define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */
38 #define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */
39
40 #define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */
41 #define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */
42
43 #define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */
44 #define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */
45
46
m1543_irq_setup(void)47 static void m1543_irq_setup(void)
48 {
49 /*
50 * The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all
51 * the possible IO sources in the M1543 are in use by us. We will
52 * use the following mapping:
53 *
54 * IRQ1 - keyboard (default set by M1543)
55 * IRQ3 - reserved for UART B (default set by M1543) (note that
56 * the schematics for the DDB Vrc-5074 board seem to
57 * indicate that IRQ3 is connected to the DS1386
58 * watchdog timer interrupt output so we might have
59 * a conflict)
60 * IRQ4 - reserved for UART A (default set by M1543)
61 * IRQ5 - parallel (default set by M1543)
62 * IRQ8 - DS1386 time of day (RTC) interrupt
63 * IRQ12 - mouse
64 */
65
66 /*
67 * Assing mouse interrupt to IRQ12
68 */
69
70 /* Enter configuration mode */
71 outb(0x51, M1543_PNP_CONFIG);
72 outb(0x23, M1543_PNP_CONFIG);
73
74 /* Select logical device 7 (Keyboard) */
75 outb(0x07, M1543_PNP_INDEX);
76 outb(0x07, M1543_PNP_DATA);
77
78 /* Select IRQ12 */
79 outb(0x72, M1543_PNP_INDEX);
80 outb(0x0c, M1543_PNP_DATA);
81
82 outb(0x30, M1543_PNP_INDEX);
83 printk("device 7, 0x30: %02x\n",inb(M1543_PNP_DATA));
84
85 outb(0x70, M1543_PNP_INDEX);
86 printk("device 7, 0x70: %02x\n",inb(M1543_PNP_DATA));
87
88 /* Leave configration mode */
89 outb(0xbb, M1543_PNP_CONFIG);
90
91
92 }
93
ddb_local0_irqdispatch(struct pt_regs * regs)94 void ddb_local0_irqdispatch(struct pt_regs *regs)
95 {
96 u32 mask;
97 int nile4_irq;
98
99 mask = nile4_get_irq_stat(0);
100
101 /* Handle the timer interrupt first */
102 #if 0
103 if (mask & (1 << NILE4_INT_GPT)) {
104 do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs);
105 mask &= ~(1 << NILE4_INT_GPT);
106 }
107 #endif
108 for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1)
109 if (mask & 1) {
110 if (nile4_irq == NILE4_INT_INTE) {
111 int i8259_irq;
112
113 nile4_clear_irq(NILE4_INT_INTE);
114 i8259_irq = nile4_i8259_iack();
115 do_IRQ(i8259_irq, regs);
116 } else
117 do_IRQ(nile4_to_irq(nile4_irq), regs);
118
119 }
120 }
121
ddb_local1_irqdispatch(void)122 void ddb_local1_irqdispatch(void)
123 {
124 printk("ddb_local1_irqdispatch called\n");
125 }
126
ddb_buserror_irq(void)127 void ddb_buserror_irq(void)
128 {
129 printk("ddb_buserror_irq called\n");
130 }
131
ddb_8254timer_irq(void)132 void ddb_8254timer_irq(void)
133 {
134 printk("ddb_8254timer_irq called\n");
135 }
136
ddb_irq_setup(void)137 void __init ddb_irq_setup(void)
138 {
139 #ifdef CONFIG_KGDB
140 if (remote_debug)
141 set_debug_traps();
142 breakpoint(); /* you may move this line to whereever you want :-) */
143 #endif
144
145 /* setup cascade interrupts */
146 setup_irq(NILE4_IRQ_BASE + NILE4_INT_INTE, &irq_cascade);
147 setup_irq(CPU_IRQ_BASE + CPU_NILE4_CASCADE, &irq_cascade);
148
149 set_except_vector(0, ddbIRQ);
150
151 nile4_irq_setup(NILE4_IRQ_BASE);
152 m1543_irq_setup();
153 init_i8259_irqs();
154
155
156 printk("CPU_IRQ_BASE: %d\n",CPU_IRQ_BASE);
157
158 mips_cpu_irq_init(CPU_IRQ_BASE);
159
160 printk("enabling 8259 cascade\n");
161
162 ddb5074_led_hex(0);
163
164 /* Enable the interrupt cascade */
165 nile4_enable_irq(NILE4_IRQ_BASE+IRQ_I8259_CASCADE);
166
167
168 }
169