1/*
2 * bagetIRQ.S: Interrupt exception dispatch code for Baget/MIPS
3 *
4 * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
5 */
6#include <asm/asm.h>
7#include <asm/mipsregs.h>
8#include <asm/regdef.h>
9#include <asm/stackframe.h>
10#include <asm/addrspace.h>
11
12	.text
13	.set    mips1
14	.set    reorder
15	.set    macro
16	.set    noat
17	.align	5
18
19NESTED(bagetIRQ, PT_SIZE, sp)
20	SAVE_ALL
21	CLI				# Important: mark KERNEL mode !
22
23	la      a1, baget_interrupt
24	.set	push
25	.set    noreorder
26	jal	a1
27	.set    pop
28	move	a0, sp
29
30	la      a1, ret_from_irq
31	jr	a1
32END(bagetIRQ)
33
34#define DBE_HANDLER       0x1C
35
36NESTED(try_read, PT_SIZE, sp)
37	mfc0	t3, CP0_STATUS		# save flags and
38	CLI				#  disable interrupts
39
40	li	t0, KSEG2
41	sltu    t1, t0, a0              # Is it KSEG2 address ?
42	beqz	t1, mapped              # No - already mapped !
43
44	move    t0, a0
45	ori	t0, 0xfff
46	xori    t0, 0xfff               # round address to page
47
48	ori     t1, t0, 0xf00           # prepare EntryLo (N,V,D,G)
49
50	mfc0    t2,   CP0_ENTRYHI       # save ASID value
51	mtc0	zero, CP0_INDEX
52	mtc0	t0,   CP0_ENTRYHI       # Load MMU values ...
53	mtc0    t1,   CP0_ENTRYLO0
54	nop                             # let it understand
55	nop
56	tlbwi				# ... and write ones
57	nop
58	nop
59	mtc0    t2,  CP0_ENTRYHI
60
61mapped:
62	la	t0, exception_handlers
63	lw	t1, DBE_HANDLER(t0)	# save real handler
64	la	t2, dbe_handler
65	sw	t2, DBE_HANDLER(t0)	# set temporary local handler
66	li	v0, -1			# default (failure) value
67
68	li	t2, 1
69	beq	t2, a1, 1f
70	li	t2, 2
71	beq	t2, a1, 2f
72	li	t2, 4
73	beq	t2, a1, 4f
74	b	out
75
761:	lbu	v0, (a0)		# byte
77	b	out
78
792:	lhu	v0, (a0)		# short
80	b	out
81
824:	lw	v0, (a0)		# word
83
84out:
85	sw	t1, DBE_HANDLER(t0)	# restore real handler
86	mtc0	t3, CP0_STATUS		# restore CPU flags
87	jr	ra
88
89dbe_handler:
90	li	v0, -1			# mark our failure
91	.set	push
92	.set	noreorder
93	b	out			# "no problems !"
94	rfe				#   return from trap
95	.set	pop
96END(try_read)
97