1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Pb1500 board setup.
5 *
6 * Copyright 2000 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30 #include <linux/config.h>
31 #include <linux/init.h>
32 #include <linux/sched.h>
33 #include <linux/ioport.h>
34 #include <linux/mm.h>
35 #include <linux/console.h>
36 #include <linux/mc146818rtc.h>
37 #include <linux/delay.h>
38
39 #include <asm/cpu.h>
40 #include <asm/bootinfo.h>
41 #include <asm/irq.h>
42 #include <asm/keyboard.h>
43 #include <asm/mipsregs.h>
44 #include <asm/reboot.h>
45 #include <asm/pgtable.h>
46 #include <asm/au1000.h>
47 #include <asm/pb1500.h>
48
49 #ifdef CONFIG_USB_OHCI
50 // Enable the workaround for the OHCI DoneHead
51 // register corruption problem.
52 #define CONFIG_AU1000_OHCI_FIX
53 #endif
54
55 #ifdef CONFIG_RTC
56 extern struct rtc_ops pb1500_rtc_ops;
57 #endif
58
board_reset(void)59 void board_reset (void)
60 {
61 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
62 au_writel(0x00000000, 0xAE00001C);
63 }
64
board_setup(void)65 void __init board_setup(void)
66 {
67 u32 pin_func;
68 u32 sys_freqctrl, sys_clksrc;
69
70
71 // set AUX clock to 12MHz * 8 = 96 MHz
72 au_writel(8, SYS_AUXPLL);
73 au_writel(0, SYS_PINSTATERD);
74 udelay(100);
75
76 #if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE)
77
78 /* GPIO201 is input for PCMCIA card detect */
79 /* GPIO203 is input for PCMCIA interrupt request */
80 au_writel(au_readl(GPIO2_DIR) & (u32)(~((1<<1)|(1<<3))), GPIO2_DIR);
81
82 /* zero and disable FREQ2 */
83 sys_freqctrl = au_readl(SYS_FREQCTRL0);
84 sys_freqctrl &= ~0xFFF00000;
85 au_writel(sys_freqctrl, SYS_FREQCTRL0);
86
87 /* zero and disable USBH/USBD clocks */
88 sys_clksrc = au_readl(SYS_CLKSRC);
89 sys_clksrc &= ~0x00007FE0;
90 au_writel(sys_clksrc, SYS_CLKSRC);
91
92 sys_freqctrl = au_readl(SYS_FREQCTRL0);
93 sys_freqctrl &= ~0xFFF00000;
94
95 sys_clksrc = au_readl(SYS_CLKSRC);
96 sys_clksrc &= ~0x00007FE0;
97
98 // FREQ2 = aux/2 = 48 MHz
99 sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
100 au_writel(sys_freqctrl, SYS_FREQCTRL0);
101
102 /*
103 * Route 48MHz FREQ2 into USB Host and/or Device
104 */
105 #ifdef CONFIG_USB_OHCI
106 sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
107 #endif
108 #ifdef CONFIG_AU1X00_USB_DEVICE
109 sys_clksrc |= ((4<<7) | (0<<6) | (0<<5));
110 #endif
111 au_writel(sys_clksrc, SYS_CLKSRC);
112
113
114 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8000);
115 #ifndef CONFIG_AU1X00_USB_DEVICE
116 // 2nd USB port is USB host
117 pin_func |= 0x8000;
118 #endif
119 au_writel(pin_func, SYS_PINFUNC);
120 #endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE)
121
122
123
124 #ifdef CONFIG_PCI
125 // Setup PCI bus controller
126 au_writel(0, Au1500_PCI_CMEM);
127 au_writel(0x00003fff, Au1500_CFG_BASE);
128 #if defined(__MIPSEB__)
129 au_writel(0xf | (2<<6) | (1<<4), Au1500_PCI_CFG);
130 #else
131 au_writel(0xf, Au1500_PCI_CFG);
132 #endif
133 au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
134 au_writel(0, Au1500_PCI_MWBASE_REV_CCL);
135 au_writel(0x02a00356, Au1500_PCI_STATCMD);
136 au_writel(0x00003c04, Au1500_PCI_HDRTYPE);
137 au_writel(0x00000008, Au1500_PCI_MBAR);
138 au_sync();
139 #endif
140
141 /* Enable sys bus clock divider when IDLE state or no bus activity. */
142 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
143
144 #ifdef CONFIG_RTC
145 rtc_ops = &pb1500_rtc_ops;
146 // Enable the RTC if not already enabled
147 if (!(au_readl(0xac000028) & 0x20)) {
148 printk("enabling clock ...\n");
149 au_writel((au_readl(0xac000028) | 0x20), 0xac000028);
150 }
151 // Put the clock in BCD mode
152 if (readl(0xac00002C) & 0x4) { /* reg B */
153 au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c);
154 au_sync();
155 }
156 #endif
157 }
158