1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Pb1000 board setup.
5 *
6 * Copyright 2000 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30 #include <linux/config.h>
31 #include <linux/init.h>
32 #include <linux/sched.h>
33 #include <linux/ioport.h>
34 #include <linux/mm.h>
35 #include <linux/console.h>
36 #include <linux/mc146818rtc.h>
37 #include <linux/delay.h>
38
39 #include <asm/cpu.h>
40 #include <asm/bootinfo.h>
41 #include <asm/irq.h>
42 #include <asm/keyboard.h>
43 #include <asm/mipsregs.h>
44 #include <asm/reboot.h>
45 #include <asm/pgtable.h>
46 #include <asm/au1000.h>
47 #include <asm/pb1000.h>
48
49 #ifdef CONFIG_USB_OHCI
50 // Enable the workaround for the OHCI DoneHead
51 // register corruption problem.
52 #define CONFIG_AU1000_OHCI_FIX
53 #endif
54
55 extern struct rtc_ops no_rtc_ops;
56
board_reset(void)57 void board_reset (void)
58 {
59 }
60
board_setup(void)61 void __init board_setup(void)
62 {
63 u32 pin_func, static_cfg0;
64 u32 sys_freqctrl, sys_clksrc;
65 u32 prid = read_c0_prid();
66
67 rtc_ops = &no_rtc_ops;
68
69 // set AUX clock to 12MHz * 8 = 96 MHz
70 au_writel(8, SYS_AUXPLL);
71 au_writel(0, SYS_PINSTATERD);
72 udelay(100);
73
74 #if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE)
75 /* zero and disable FREQ2 */
76 sys_freqctrl = au_readl(SYS_FREQCTRL0);
77 sys_freqctrl &= ~0xFFF00000;
78 au_writel(sys_freqctrl, SYS_FREQCTRL0);
79
80 /* zero and disable USBH/USBD clocks */
81 sys_clksrc = au_readl(SYS_CLKSRC);
82 sys_clksrc &= ~0x00007FE0;
83 au_writel(sys_clksrc, SYS_CLKSRC);
84
85 sys_freqctrl = au_readl(SYS_FREQCTRL0);
86 sys_freqctrl &= ~0xFFF00000;
87
88 sys_clksrc = au_readl(SYS_CLKSRC);
89 sys_clksrc &= ~0x00007FE0;
90
91 switch (prid & 0x000000FF)
92 {
93 case 0x00: /* DA */
94 case 0x01: /* HA */
95 case 0x02: /* HB */
96 /* CPU core freq to 48MHz to slow it way down... */
97 au_writel(4, SYS_CPUPLL);
98
99 /*
100 * Setup 48MHz FREQ2 from CPUPLL for USB Host
101 */
102 /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
103 sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
104 au_writel(sys_freqctrl, SYS_FREQCTRL0);
105
106 /* CPU core freq to 384MHz */
107 au_writel(0x20, SYS_CPUPLL);
108
109 printk("Au1000: 48MHz OHCI workaround enabled\n");
110 break;
111
112 default: /* HC and newer */
113 // FREQ2 = aux/2 = 48 MHz
114 sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
115 au_writel(sys_freqctrl, SYS_FREQCTRL0);
116 break;
117 }
118
119 /*
120 * Route 48MHz FREQ2 into USB Host and/or Device
121 */
122 #ifdef CONFIG_USB_OHCI
123 sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
124 #endif
125 #ifdef CONFIG_AU1X00_USB_DEVICE
126 sys_clksrc |= ((4<<7) | (0<<6) | (0<<5));
127 #endif
128 au_writel(sys_clksrc, SYS_CLKSRC);
129
130 // configure pins GPIO[14:9] as GPIO
131 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
132
133 #ifndef CONFIG_AU1X00_USB_DEVICE
134 // 2nd USB port is USB host
135 pin_func |= 0x8000;
136 #endif
137 au_writel(pin_func, SYS_PINFUNC);
138 au_writel(0x2800, SYS_TRIOUTCLR);
139 au_writel(0x0030, SYS_OUTPUTCLR);
140 #endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE)
141
142 // make gpio 15 an input (for interrupt line)
143 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x100);
144 // we don't need I2S, so make it available for GPIO[31:29]
145 pin_func |= (1<<5);
146 au_writel(pin_func, SYS_PINFUNC);
147
148 au_writel(0x8000, SYS_TRIOUTCLR);
149
150 static_cfg0 = au_readl(MEM_STCFG0) & (u32)(~0xc00);
151 au_writel(static_cfg0, MEM_STCFG0);
152
153 // configure RCE2* for LCD
154 au_writel(0x00000004, MEM_STCFG2);
155
156 // MEM_STTIME2
157 au_writel(0x09000000, MEM_STTIME2);
158
159 // Set 32-bit base address decoding for RCE2*
160 au_writel(0x10003ff0, MEM_STADDR2);
161
162 // PCI CPLD setup
163 // expand CE0 to cover PCI
164 au_writel(0x11803e40, MEM_STADDR1);
165
166 // burst visibility on
167 au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
168
169 au_writel(0x83, MEM_STCFG1); // ewait enabled, flash timing
170 au_writel(0x33030a10, MEM_STTIME1); // slower timing for FPGA
171
172 /* setup the static bus controller */
173 au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
174 au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
175 au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
176
177 #ifdef CONFIG_PCI
178 au_writel(0, PCI_BRIDGE_CONFIG); // set extend byte to 0
179 au_writel(0, SDRAM_MBAR); // set mbar to 0
180 au_writel(0x2, SDRAM_CMD); // enable memory accesses
181 au_sync_delay(1);
182 #endif
183
184 /* Enable Au1000 BCLK switching - note: sed1356 must not use
185 * its BCLK (Au1000 LCLK) for any timings */
186 switch (prid & 0x000000FF)
187 {
188 case 0x00: /* DA */
189 case 0x01: /* HA */
190 case 0x02: /* HB */
191 break;
192 default: /* HC and newer */
193 /* Enable sys bus clock divider when IDLE state or no bus
194 activity. */
195 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
196 break;
197 }
198 }
199