1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Cogent CSB250 board setup.
5 *
6 * Copyright 2002 Cogent Computer Systems, Inc.
7 * dan@embeddededge.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29 #include <linux/config.h>
30 #include <linux/init.h>
31 #include <linux/sched.h>
32 #include <linux/ioport.h>
33 #include <linux/mm.h>
34 #include <linux/console.h>
35 #include <linux/mc146818rtc.h>
36 #include <linux/delay.h>
37
38 #include <asm/cpu.h>
39 #include <asm/bootinfo.h>
40 #include <asm/irq.h>
41 #include <asm/keyboard.h>
42 #include <asm/mipsregs.h>
43 #include <asm/reboot.h>
44 #include <asm/pgtable.h>
45 #include <asm/au1000.h>
46 #include <asm/csb250.h>
47
48 #ifdef CONFIG_USB_OHCI
49 // Enable the workaround for the OHCI DoneHead
50 // register corruption problem.
51 #define CONFIG_AU1000_OHCI_FIX
52 #endif
53
54 #ifdef CONFIG_RTC
55 extern struct rtc_ops csb250_rtc_ops;
56 #endif
57
58 extern int (*board_pci_idsel)(unsigned int devsel, int assert);
59 int csb250_pci_idsel(unsigned int devsel, int assert);
60
board_setup(void)61 void __init board_setup(void)
62 {
63 u32 pin_func, pin_val;
64 u32 sys_freqctrl, sys_clksrc;
65
66
67 // set AUX clock to 12MHz * 8 = 96 MHz
68 au_writel(8, SYS_AUXPLL);
69 au_writel(0, SYS_PINSTATERD);
70 udelay(100);
71
72 #if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE)
73
74 /* GPIO201 is input for PCMCIA card detect */
75 /* GPIO203 is input for PCMCIA interrupt request */
76 au_writel(au_readl(GPIO2_DIR) & (u32)(~((1<<1)|(1<<3))), GPIO2_DIR);
77
78 /* zero and disable FREQ2 */
79 sys_freqctrl = au_readl(SYS_FREQCTRL0);
80 sys_freqctrl &= ~0xFFF00000;
81 au_writel(sys_freqctrl, SYS_FREQCTRL0);
82
83 /* zero and disable USBH/USBD clocks */
84 sys_clksrc = au_readl(SYS_CLKSRC);
85 sys_clksrc &= ~0x00007FE0;
86 au_writel(sys_clksrc, SYS_CLKSRC);
87
88 sys_freqctrl = au_readl(SYS_FREQCTRL0);
89 sys_freqctrl &= ~0xFFF00000;
90
91 sys_clksrc = au_readl(SYS_CLKSRC);
92 sys_clksrc &= ~0x00007FE0;
93
94 // FREQ2 = aux/2 = 48 MHz
95 sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
96 au_writel(sys_freqctrl, SYS_FREQCTRL0);
97
98 /*
99 * Route 48MHz FREQ2 into USB Host and/or Device
100 */
101 #ifdef CONFIG_USB_OHCI
102 sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
103 #endif
104 #ifdef CONFIG_AU1X00_USB_DEVICE
105 sys_clksrc |= ((4<<7) | (0<<6) | (0<<5));
106 #endif
107 au_writel(sys_clksrc, SYS_CLKSRC);
108
109
110 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8000);
111 #ifndef CONFIG_AU1X00_USB_DEVICE
112 // 2nd USB port is USB host
113 pin_func |= 0x8000;
114 #endif
115 au_writel(pin_func, SYS_PINFUNC);
116 #endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE)
117
118 /* Configure GPIO2....it's used by PCI among other things.
119 */
120
121 /* Make everything but GP200 (PCI RST) an input until we get
122 * the pins set correctly.
123 */
124 au_writel(0x00000001, GPIO2_DIR);
125
126 /* Set the pins used for output.
127 * A zero bit will leave PCI reset, LEDs off, power up USB,
128 * IDSEL disabled.
129 */
130 pin_val = ((3 << 30) | (7 << 19) | (1 << 17) | (1 << 16));
131 au_writel(pin_val, GPIO2_OUTPUT);
132
133 /* Set the output direction.
134 */
135 pin_val = ((3 << 14) | (7 << 3) | (1 << 1) | (1 << 0));
136 au_writel(pin_val, GPIO2_DIR);
137
138 #ifdef CONFIG_PCI
139 /* Use FREQ1 for the PCI output clock. We use the
140 * CPU clock of 384 MHz divided by 12 to get 32 MHz PCI.
141 * If Michael changes the CPU speed, we need to adjust
142 * that here as well :-).
143 */
144
145 /* zero and disable FREQ1
146 */
147 sys_freqctrl = au_readl(SYS_FREQCTRL0);
148 sys_freqctrl &= ~0x000ffc00;
149 au_writel(sys_freqctrl, SYS_FREQCTRL0);
150
151 /* zero and disable PCI clock
152 */
153 sys_clksrc = au_readl(SYS_CLKSRC);
154 sys_clksrc &= ~0x000f8000;
155 au_writel(sys_clksrc, SYS_CLKSRC);
156
157 /* Get current values (which really should match above).
158 */
159 sys_freqctrl = au_readl(SYS_FREQCTRL0);
160 sys_freqctrl &= ~0x000ffc00;
161
162 sys_clksrc = au_readl(SYS_CLKSRC);
163 sys_clksrc &= ~0x000f8000;
164
165 /* FREQ1 = cpu/12 = 32 MHz
166 */
167 sys_freqctrl |= ((5<<12) | (1<<11) | (0<<10));
168 au_writel(sys_freqctrl, SYS_FREQCTRL0);
169
170 /* Just connect the clock without further dividing.
171 */
172 sys_clksrc |= ((3<<17) | (0<<16) | (0<<15));
173 au_writel(sys_clksrc, SYS_CLKSRC);
174
175 udelay(1);
176
177 /* Now that clocks should be running, take PCI out of reset.
178 */
179 pin_val = au_readl(GPIO2_OUTPUT);
180 pin_val |= ((1 << 16) | 1);
181 au_writel(pin_val, GPIO2_OUTPUT);
182
183 // Setup PCI bus controller
184 au_writel(0, Au1500_PCI_CMEM);
185 au_writel(0x00003fff, Au1500_CFG_BASE);
186
187 /* We run big endian without any of the software byte swapping,
188 * so configure the PCI bridge to help us out.
189 */
190 au_writel(0xf | (2<<6) | (1<<5) | (1<<4), Au1500_PCI_CFG);
191
192 au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
193 au_writel(0, Au1500_PCI_MWBASE_REV_CCL);
194 au_writel(0x02a00356, Au1500_PCI_STATCMD);
195 au_writel(0x00003c04, Au1500_PCI_HDRTYPE);
196 au_writel(0x00000008, Au1500_PCI_MBAR);
197 au_sync();
198
199 board_pci_idsel = csb250_pci_idsel;
200 #endif
201
202 /* Enable sys bus clock divider when IDLE state or no bus activity. */
203 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
204
205 #ifdef CONFIG_RTC
206 rtc_ops = &csb250_rtc_ops;
207 // Enable the RTC if not already enabled
208 if (!(au_readl(0xac000028) & 0x20)) {
209 printk("enabling clock ...\n");
210 au_writel((au_readl(0xac000028) | 0x20), 0xac000028);
211 }
212 // Put the clock in BCD mode
213 if (readl(0xac00002C) & 0x4) { /* reg B */
214 au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c);
215 au_sync();
216 }
217 #endif
218 }
219
220 /* The IDSEL is selected in the GPIO2 register. We will make device
221 * 12 appear in slot 0 and device 13 appear in slot 1.
222 */
223 int
csb250_pci_idsel(unsigned int devsel,int assert)224 csb250_pci_idsel(unsigned int devsel, int assert)
225 {
226 int retval;
227 unsigned int gpio2_pins;
228
229 retval = 1;
230
231 /* First, disable both selects, then assert the one requested.
232 */
233 au_writel(0xc000c000, GPIO2_OUTPUT);
234 au_sync();
235
236 if (assert) {
237 if (devsel == 12)
238 gpio2_pins = 0x40000000;
239 else if (devsel == 13)
240 gpio2_pins = 0x80000000;
241 else {
242 gpio2_pins = 0xc000c000;
243 retval = 0;
244 }
245 au_writel(gpio2_pins, GPIO2_OUTPUT);
246 }
247 au_sync();
248
249 return retval;
250 }
251