1 /*
2 *
3 * Copyright (C) 2001 MontaVista Software, ppopov@mvista.com
4 * Copied and modified Carsten Langgaard's time.c
5 *
6 * Carsten Langgaard, carstenl@mips.com
7 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
8 *
9 * ########################################################################
10 *
11 * This program is free software; you can distribute it and/or modify it
12 * under the terms of the GNU General Public License (Version 2) as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
23 *
24 * ########################################################################
25 *
26 * Setting up the clock on the MIPS boards.
27 *
28 * Update. Always configure the kernel with CONFIG_NEW_TIME_C. This
29 * will use the user interface gettimeofday() functions from the
30 * arch/mips/kernel/time.c, and we provide the clock interrupt processing
31 * and the timer offset compute functions. If CONFIG_PM is selected,
32 * we also ensure the 32KHz timer is available. -- Dan
33 */
34
35 #include <linux/types.h>
36 #include <linux/config.h>
37 #include <linux/init.h>
38 #include <linux/kernel_stat.h>
39 #include <linux/sched.h>
40 #include <linux/spinlock.h>
41
42 #include <asm/compiler.h>
43 #include <asm/mipsregs.h>
44 #include <asm/ptrace.h>
45 #include <asm/time.h>
46 #include <asm/hardirq.h>
47 #include <asm/div64.h>
48 #include <asm/au1000.h>
49
50 #include <linux/mc146818rtc.h>
51 #include <linux/timex.h>
52
53 extern void startup_match20_interrupt(void);
54 extern void do_softirq(void);
55 extern volatile unsigned long wall_jiffies;
56 unsigned long missed_heart_beats = 0;
57
58 static unsigned long r4k_offset; /* Amount to increment compare reg each time */
59 static unsigned long r4k_cur; /* What counter should be at next timer irq */
60 extern rwlock_t xtime_lock;
61 int no_au1xxx_32khz;
62 void (*au1k_wait_ptr)(void);
63
64 /* Cycle counter value at the previous timer interrupt.. */
65 static unsigned int timerhi = 0, timerlo = 0;
66
67 #ifdef CONFIG_PM
68 #define MATCH20_INC 328
69 extern void startup_match20_interrupt(void);
70 static unsigned long last_pc0, last_match20;
71 #endif
72
73 static spinlock_t time_lock = SPIN_LOCK_UNLOCKED;
74
ack_r4ktimer(unsigned long newval)75 static inline void ack_r4ktimer(unsigned long newval)
76 {
77 write_c0_compare(newval);
78 }
79
80 /*
81 * There are a lot of conceptually broken versions of the MIPS timer interrupt
82 * handler floating around. This one is rather different, but the algorithm
83 * is provably more robust.
84 */
85 unsigned long wtimer;
mips_timer_interrupt(struct pt_regs * regs)86 void mips_timer_interrupt(struct pt_regs *regs)
87 {
88 int irq = 63;
89 unsigned long count;
90 int cpu = smp_processor_id();
91
92 irq_enter(cpu, irq);
93 kstat.irqs[cpu][irq]++;
94
95 if (r4k_offset == 0)
96 goto null;
97
98 do {
99 count = read_c0_count();
100 timerhi += (count < timerlo); /* Wrap around */
101 timerlo = count;
102
103 kstat.irqs[0][irq]++;
104 do_timer(regs);
105 r4k_cur += r4k_offset;
106 ack_r4ktimer(r4k_cur);
107
108 } while (((unsigned long)read_c0_count()
109 - r4k_cur) < 0x7fffffff);
110
111 irq_exit(cpu, irq);
112
113 if (softirq_pending(cpu))
114 do_softirq();
115 return;
116
117 null:
118 ack_r4ktimer(0);
119 }
120
121 #ifdef CONFIG_PM
counter0_irq(int irq,void * dev_id,struct pt_regs * regs)122 void counter0_irq(int irq, void *dev_id, struct pt_regs *regs)
123 {
124 unsigned long pc0;
125 int time_elapsed;
126 static int jiffie_drift = 0;
127
128 kstat.irqs[0][irq]++;
129 if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
130 /* should never happen! */
131 printk(KERN_WARNING "counter 0 w status eror\n");
132 return;
133 }
134
135 pc0 = au_readl(SYS_TOYREAD);
136 if (pc0 < last_match20) {
137 /* counter overflowed */
138 time_elapsed = (0xffffffff - last_match20) + pc0;
139 }
140 else {
141 time_elapsed = pc0 - last_match20;
142 }
143
144 while (time_elapsed > 0) {
145 do_timer(regs);
146 time_elapsed -= MATCH20_INC;
147 last_match20 += MATCH20_INC;
148 jiffie_drift++;
149 }
150
151 last_pc0 = pc0;
152 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
153 au_sync();
154
155 /* our counter ticks at 10.009765625 ms/tick, we we're running
156 * almost 10uS too slow per tick.
157 */
158
159 if (jiffie_drift >= 999) {
160 jiffie_drift -= 999;
161 do_timer(regs); /* increment jiffies by one */
162 }
163 }
164
165 /* When we wakeup from sleep, we have to "catch up" on all of the
166 * timer ticks we have missed.
167 */
168 void
wakeup_counter0_adjust(void)169 wakeup_counter0_adjust(void)
170 {
171 unsigned long pc0;
172 int time_elapsed;
173
174 pc0 = au_readl(SYS_TOYREAD);
175 if (pc0 < last_match20) {
176 /* counter overflowed */
177 time_elapsed = (0xffffffff - last_match20) + pc0;
178 }
179 else {
180 time_elapsed = pc0 - last_match20;
181 }
182
183 while (time_elapsed > 0) {
184 time_elapsed -= MATCH20_INC;
185 last_match20 += MATCH20_INC;
186 }
187
188 last_pc0 = pc0;
189 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
190 au_sync();
191
192 }
193
194 /* This is just for debugging to set the timer for a sleep delay.
195 */
196 void
wakeup_counter0_set(int ticks)197 wakeup_counter0_set(int ticks)
198 {
199 unsigned long pc0;
200
201 pc0 = au_readl(SYS_TOYREAD);
202 last_pc0 = pc0;
203 au_writel(last_match20 + (MATCH20_INC * ticks), SYS_TOYMATCH2);
204 au_sync();
205 }
206 #endif
207
208 /* I haven't found anyone that doesn't use a 12 MHz source clock,
209 * but just in case.....
210 */
211 #ifdef CONFIG_AU1000_SRC_CLK
212 #define AU1000_SRC_CLK CONFIG_AU1000_SRC_CLK
213 #else
214 #define AU1000_SRC_CLK 12000000
215 #endif
216
217 /*
218 * We read the real processor speed from the PLL. This is important
219 * because it is more accurate than computing it from the 32KHz
220 * counter, if it exists. If we don't have an accurate processor
221 * speed, all of the peripherals that derive their clocks based on
222 * this advertised speed will introduce error and sometimes not work
223 * properly. This function is futher convoluted to still allow configurations
224 * to do that in case they have really, really old silicon with a
225 * write-only PLL register, that we need the 32KHz when power management
226 * "wait" is enabled, and we need to detect if the 32KHz isn't present
227 * but requested......got it? :-) -- Dan
228 */
cal_r4koff(void)229 unsigned long cal_r4koff(void)
230 {
231 unsigned long count;
232 unsigned long cpu_speed;
233 unsigned long flags;
234 unsigned long counter;
235
236 spin_lock_irqsave(&time_lock, flags);
237
238 /* Power management cares if we don't have a 32KHz counter.
239 */
240 no_au1xxx_32khz = 0;
241 counter = au_readl(SYS_COUNTER_CNTRL);
242 if (counter & SYS_CNTRL_E0) {
243 int trim_divide = 16;
244
245 au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL);
246
247 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
248 /* RTC now ticks at 32.768/16 kHz */
249 au_writel(trim_divide-1, SYS_RTCTRIM);
250 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
251
252 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
253 au_writel (0, SYS_TOYWRITE);
254 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
255
256 #if defined(CONFIG_AU1000_USE32K)
257 {
258 unsigned long start, end;
259
260 start = au_readl(SYS_RTCREAD);
261 start += 2;
262 /* wait for the beginning of a new tick
263 */
264 while (au_readl(SYS_RTCREAD) < start);
265
266 /* Start r4k counter.
267 */
268 write_c0_count(0);
269
270 /* Wait 0.5 seconds.
271 */
272 end = start + (32768 / trim_divide)/2;
273
274 while (end > au_readl(SYS_RTCREAD));
275
276 count = read_c0_count();
277 cpu_speed = count * 2;
278 }
279 #else
280 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
281 AU1000_SRC_CLK;
282 count = cpu_speed / 2;
283 #endif
284 }
285 else {
286 /* The 32KHz oscillator isn't running, so assume there
287 * isn't one and grab the processor speed from the PLL.
288 * NOTE: some old silicon doesn't allow reading the PLL.
289 */
290 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
291 count = cpu_speed / 2;
292 no_au1xxx_32khz = 1;
293 }
294 mips_hpt_frequency = count;
295 // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
296 set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
297 spin_unlock_irqrestore(&time_lock, flags);
298 return (cpu_speed / HZ);
299 }
300
301 /* This is for machines which generate the exact clock. */
302 #define USECS_PER_JIFFY (1000000/HZ)
303 #define USECS_PER_JIFFY_FRAC (0x100000000*1000000/HZ&0xffffffff)
304
305
306 static unsigned long
div64_32(unsigned long v1,unsigned long v2,unsigned long v3)307 div64_32(unsigned long v1, unsigned long v2, unsigned long v3)
308 {
309 unsigned long r0;
310 do_div64_32(r0, v1, v2, v3);
311 return r0;
312 }
313
do_fast_cp0_gettimeoffset(void)314 static unsigned long do_fast_cp0_gettimeoffset(void)
315 {
316 u32 count;
317 unsigned long res, tmp;
318 unsigned long r0;
319
320 /* Last jiffy when do_fast_gettimeoffset() was called. */
321 static unsigned long last_jiffies=0;
322 unsigned long quotient;
323
324 /*
325 * Cached "1/(clocks per usec)*2^32" value.
326 * It has to be recalculated once each jiffy.
327 */
328 static unsigned long cached_quotient=0;
329
330 tmp = jiffies;
331
332 quotient = cached_quotient;
333
334 if (tmp && last_jiffies != tmp) {
335 last_jiffies = tmp;
336 if (last_jiffies != 0) {
337 r0 = div64_32(timerhi, timerlo, tmp);
338 quotient = div64_32(USECS_PER_JIFFY, USECS_PER_JIFFY_FRAC, r0);
339 cached_quotient = quotient;
340 }
341 }
342
343 /* Get last timer tick in absolute kernel time */
344 count = read_c0_count();
345
346 /* .. relative to previous jiffy (32 bits is enough) */
347 count -= timerlo;
348
349 __asm__("multu\t%1,%2\n\t"
350 "mfhi\t%0"
351 : "=r" (res)
352 : "r" (count), "r" (quotient)
353 : "hi", "lo", GCC_REG_ACCUM);
354
355 /*
356 * Due to possible jiffies inconsistencies, we need to check
357 * the result so that we'll get a timer that is monotonic.
358 */
359 if (res >= USECS_PER_JIFFY)
360 res = USECS_PER_JIFFY-1;
361
362 return res;
363 }
364
365 #ifdef CONFIG_PM
do_fast_pm_gettimeoffset(void)366 static unsigned long do_fast_pm_gettimeoffset(void)
367 {
368 unsigned long pc0;
369 unsigned long offset;
370
371 pc0 = au_readl(SYS_TOYREAD);
372 au_sync();
373 offset = pc0 - last_pc0;
374 if (offset > 2*MATCH20_INC) {
375 printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n",
376 (unsigned)offset, (unsigned)last_pc0,
377 (unsigned)last_match20, (unsigned)pc0);
378 }
379 offset = (unsigned long)((offset * 305) / 10);
380 return offset;
381 }
382 #endif
383
au1xxx_timer_setup(void)384 void __init au1xxx_timer_setup(void)
385 {
386 unsigned int est_freq;
387 extern unsigned long (*do_gettimeoffset)(void);
388 extern void au1k_wait(void);
389
390 printk("calculating r4koff... ");
391 r4k_offset = cal_r4koff();
392 printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
393
394 //est_freq = 2*r4k_offset*HZ;
395 est_freq = r4k_offset*HZ;
396 est_freq += 5000; /* round */
397 est_freq -= est_freq%10000;
398 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
399 (est_freq%1000000)*100/1000000);
400 set_au1x00_speed(est_freq);
401 set_au1x00_lcd_clock(); // program the LCD clock
402
403 r4k_cur = (read_c0_count() + r4k_offset);
404 write_c0_compare(r4k_cur);
405
406 /* no RTC on the pb1000 */
407 xtime.tv_sec = 0;
408 xtime.tv_usec = 0;
409
410 #ifdef CONFIG_PM
411 /*
412 * setup counter 0, since it keeps ticking after a
413 * 'wait' instruction has been executed. The CP0 timer and
414 * counter 1 do NOT continue running after 'wait'
415 *
416 * It's too early to call request_irq() here, so we handle
417 * counter 0 interrupt as a special irq and it doesn't show
418 * up under /proc/interrupts.
419 *
420 * Check to ensure we really have a 32KHz oscillator before
421 * we do this.
422 */
423 if (no_au1xxx_32khz) {
424 unsigned int c0_status;
425
426 printk("WARNING: no 32KHz clock found.\n");
427 do_gettimeoffset = do_fast_cp0_gettimeoffset;
428
429 /* Ensure we get CPO_COUNTER interrupts.
430 */
431 c0_status = read_c0_status();
432 c0_status |= IE_IRQ5;
433 write_c0_status(c0_status);
434 }
435 else {
436 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
437 au_writel(0, SYS_TOYWRITE);
438 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
439
440 au_writel(au_readl(SYS_WAKEMSK) | (1<<8), SYS_WAKEMSK);
441 au_writel(~0, SYS_WAKESRC);
442 au_sync();
443 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
444
445 /* setup match20 to interrupt once every 10ms */
446 last_pc0 = last_match20 = au_readl(SYS_TOYREAD);
447 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
448 au_sync();
449 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
450 startup_match20_interrupt();
451
452 do_gettimeoffset = do_fast_pm_gettimeoffset;
453
454 /* We can use the real 'wait' instruction.
455 */
456 au1k_wait_ptr = au1k_wait;
457 }
458
459 #else
460 /* We have to do this here instead of in timer_init because
461 * the generic code in arch/mips/kernel/time.c will write
462 * over our function pointer.
463 */
464 do_gettimeoffset = do_fast_cp0_gettimeoffset;
465 #endif
466 }
467
au1xxx_time_init(void)468 void __init au1xxx_time_init(void)
469 {
470 }
471