1 /*
2 * BRIEF MODULE DESCRIPTION
3 * Au1000 Power Management routines.
4 *
5 * Copyright 2001 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * Some of the routines are right out of init/main.c, whose
10 * copyrights apply here.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32
33 #include <linux/init.h>
34 #include <linux/pm.h>
35 #include <linux/slab.h>
36 #include <linux/sysctl.h>
37
38 #include <asm/string.h>
39 #include <asm/uaccess.h>
40 #include <asm/io.h>
41 #include <asm/system.h>
42 #include <asm/au1000.h>
43
44 #define DEBUG 1
45 #ifdef DEBUG
46 # define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
47 #else
48 # define DPRINTK(fmt, args...)
49 #endif
50
51 static void calibrate_delay(void);
52
53 extern void set_au1x00_speed(unsigned int new_freq);
54 extern unsigned int get_au1x00_speed(void);
55 extern unsigned long get_au1x00_uart_baud_base(void);
56 extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
57 extern unsigned long save_local_and_disable(int controller);
58 extern void restore_local_and_enable(int controller, unsigned long mask);
59 extern void local_enable_irq(unsigned int irq_nr);
60
61 /* Quick acpi hack. This will have to change! */
62 #define CTL_ACPI 9999
63 #define ACPI_S1_SLP_TYP 19
64 #define ACPI_SLEEP 21
65
66 #ifdef CONFIG_PM
67
68 static spinlock_t pm_lock = SPIN_LOCK_UNLOCKED;
69
70 /* We need to save/restore a bunch of core registers that are
71 * either volatile or reset to some state across a processor sleep.
72 * If reading a register doesn't provide a proper result for a
73 * later restore, we have to provide a function for loading that
74 * register and save a copy.
75 *
76 * We only have to save/restore registers that aren't otherwise
77 * done as part of a driver pm_* function.
78 */
79 static uint sleep_aux_pll_cntrl;
80 static uint sleep_cpu_pll_cntrl;
81 static uint sleep_pin_function;
82 static uint sleep_uart0_inten;
83 static uint sleep_uart0_fifoctl;
84 static uint sleep_uart0_linectl;
85 static uint sleep_uart0_clkdiv;
86 static uint sleep_uart0_enable;
87 static uint sleep_usbhost_enable;
88 static uint sleep_usbdev_enable;
89 static uint sleep_static_memctlr[4][3];
90
91 /* Define this to cause the value you write to /proc/sys/pm/sleep to
92 * set the TOY timer for the amount of time you want to sleep.
93 * This is done mainly for testing, but may be useful in other cases.
94 * The value is number of 32KHz ticks to sleep.
95 */
96 #define SLEEP_TEST_TIMEOUT 1
97 #ifdef SLEEP_TEST_TIMEOUT
98 static int sleep_ticks;
99 void wakeup_counter0_set(int ticks);
100 #endif
101
102 static void
save_core_regs(void)103 save_core_regs(void)
104 {
105 extern void save_au1xxx_intctl(void);
106 extern void pm_eth0_shutdown(void);
107
108 /* Do the serial ports.....these really should be a pm_*
109 * registered function by the driver......but of course the
110 * standard serial driver doesn't understand our Au1xxx
111 * unique registers.
112 */
113 sleep_uart0_inten = au_readl(UART0_ADDR + UART_IER);
114 sleep_uart0_fifoctl = au_readl(UART0_ADDR + UART_FCR);
115 sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR);
116 sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK);
117 sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL);
118
119 /* Shutdown USB host/device.
120 */
121 sleep_usbhost_enable = au_readl(USB_HOST_CONFIG);
122
123 /* There appears to be some undocumented reset register....
124 */
125 au_writel(0, 0xb0100004); au_sync();
126 au_writel(0, USB_HOST_CONFIG); au_sync();
127
128 sleep_usbdev_enable = au_readl(USBD_ENABLE);
129 au_writel(0, USBD_ENABLE); au_sync();
130
131 /* Save interrupt controller state.
132 */
133 save_au1xxx_intctl();
134
135 /* Clocks and PLLs.
136 */
137 sleep_aux_pll_cntrl = au_readl(SYS_AUXPLL);
138
139 /* We don't really need to do this one, but unless we
140 * write it again it won't have a valid value if we
141 * happen to read it.
142 */
143 sleep_cpu_pll_cntrl = au_readl(SYS_CPUPLL);
144
145 sleep_pin_function = au_readl(SYS_PINFUNC);
146
147 /* Save the static memory controller configuration.
148 */
149 sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0);
150 sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0);
151 sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0);
152 sleep_static_memctlr[1][0] = au_readl(MEM_STCFG1);
153 sleep_static_memctlr[1][1] = au_readl(MEM_STTIME1);
154 sleep_static_memctlr[1][2] = au_readl(MEM_STADDR1);
155 sleep_static_memctlr[2][0] = au_readl(MEM_STCFG2);
156 sleep_static_memctlr[2][1] = au_readl(MEM_STTIME2);
157 sleep_static_memctlr[2][2] = au_readl(MEM_STADDR2);
158 sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3);
159 sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3);
160 sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3);
161 }
162
163 static void
restore_core_regs(void)164 restore_core_regs(void)
165 {
166 extern void restore_au1xxx_intctl(void);
167 extern void wakeup_counter0_adjust(void);
168
169 au_writel(sleep_aux_pll_cntrl, SYS_AUXPLL); au_sync();
170 au_writel(sleep_cpu_pll_cntrl, SYS_CPUPLL); au_sync();
171 au_writel(sleep_pin_function, SYS_PINFUNC); au_sync();
172
173 /* Restore the static memory controller configuration.
174 */
175 au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
176 au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
177 au_writel(sleep_static_memctlr[0][2], MEM_STADDR0);
178 au_writel(sleep_static_memctlr[1][0], MEM_STCFG1);
179 au_writel(sleep_static_memctlr[1][1], MEM_STTIME1);
180 au_writel(sleep_static_memctlr[1][2], MEM_STADDR1);
181 au_writel(sleep_static_memctlr[2][0], MEM_STCFG2);
182 au_writel(sleep_static_memctlr[2][1], MEM_STTIME2);
183 au_writel(sleep_static_memctlr[2][2], MEM_STADDR2);
184 au_writel(sleep_static_memctlr[3][0], MEM_STCFG3);
185 au_writel(sleep_static_memctlr[3][1], MEM_STTIME3);
186 au_writel(sleep_static_memctlr[3][2], MEM_STADDR3);
187
188 /* Enable the UART if it was enabled before sleep.
189 * I guess I should define module control bits........
190 */
191 if (sleep_uart0_enable & 0x02) {
192 au_writel(0, UART0_ADDR + UART_MOD_CNTRL); au_sync();
193 au_writel(1, UART0_ADDR + UART_MOD_CNTRL); au_sync();
194 au_writel(3, UART0_ADDR + UART_MOD_CNTRL); au_sync();
195 au_writel(sleep_uart0_inten, UART0_ADDR + UART_IER); au_sync();
196 au_writel(sleep_uart0_fifoctl, UART0_ADDR + UART_FCR); au_sync();
197 au_writel(sleep_uart0_linectl, UART0_ADDR + UART_LCR); au_sync();
198 au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync();
199 }
200
201 restore_au1xxx_intctl();
202 wakeup_counter0_adjust();
203 }
204
205 unsigned long suspend_mode;
206
wakeup_from_suspend(void)207 void wakeup_from_suspend(void)
208 {
209 suspend_mode = 0;
210 }
211
au_sleep(void)212 int au_sleep(void)
213 {
214 unsigned long wakeup, flags;
215 extern void save_and_sleep(void);
216
217 spin_lock_irqsave(&pm_lock,flags);
218
219 save_core_regs();
220
221 flush_cache_all();
222
223 /** The code below is all system dependent and we should probably
224 ** have a function call out of here to set this up. You need
225 ** to configure the GPIO or timer interrupts that will bring
226 ** you out of sleep.
227 ** For testing, the TOY counter wakeup is useful.
228 **/
229
230 #if 0
231 au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD);
232
233 /* gpio 6 can cause a wake up event */
234 wakeup = au_readl(SYS_WAKEMSK);
235 wakeup &= ~(1 << 8); /* turn off match20 wakeup */
236 wakeup |= 1 << 6; /* turn on gpio 6 wakeup */
237 #else
238 /* For testing, allow match20 to wake us up.
239 */
240 #ifdef SLEEP_TEST_TIMEOUT
241 wakeup_counter0_set(sleep_ticks);
242 #endif
243 wakeup = 1 << 8; /* turn on match20 wakeup */
244 wakeup = 0;
245 #endif
246 au_writel(1, SYS_WAKESRC); /* clear cause */
247 au_sync();
248 au_writel(wakeup, SYS_WAKEMSK);
249 au_sync();
250
251 save_and_sleep();
252
253 /* after a wakeup, the cpu vectors back to 0x1fc00000 so
254 * it's up to the boot code to get us back here.
255 */
256 restore_core_regs();
257 spin_unlock_irqrestore(&pm_lock, flags);
258 return 0;
259 }
260
pm_do_sleep(ctl_table * ctl,int write,struct file * file,void * buffer,size_t * len)261 static int pm_do_sleep(ctl_table * ctl, int write, struct file *file,
262 void *buffer, size_t * len)
263 {
264 int retval = 0;
265 #ifdef SLEEP_TEST_TIMEOUT
266 #define TMPBUFLEN2 16
267 char buf[TMPBUFLEN2], *p;
268 #endif
269
270 if (!write) {
271 *len = 0;
272 } else {
273 #ifdef SLEEP_TEST_TIMEOUT
274 if (*len > TMPBUFLEN2 - 1) {
275 return -EFAULT;
276 }
277 if (copy_from_user(buf, buffer, *len)) {
278 return -EFAULT;
279 }
280 buf[*len] = 0;
281 p = buf;
282 sleep_ticks = simple_strtoul(p, &p, 0);
283 #endif
284 retval = pm_send_all(PM_SUSPEND, (void *) 2);
285
286 if (retval)
287 return retval;
288
289 au_sleep();
290 retval = pm_send_all(PM_RESUME, (void *) 0);
291 }
292 return retval;
293 }
294
pm_do_suspend(ctl_table * ctl,int write,struct file * file,void * buffer,size_t * len)295 static int pm_do_suspend(ctl_table * ctl, int write, struct file *file,
296 void *buffer, size_t * len)
297 {
298 int retval = 0;
299 void au1k_wait(void);
300
301 if (!write) {
302 *len = 0;
303 } else {
304 retval = pm_send_all(PM_SUSPEND, (void *) 2);
305 if (retval)
306 return retval;
307 suspend_mode = 1;
308 au1k_wait();
309 retval = pm_send_all(PM_RESUME, (void *) 0);
310 }
311 return retval;
312 }
313
314
pm_do_freq(ctl_table * ctl,int write,struct file * file,void * buffer,size_t * len)315 static int pm_do_freq(ctl_table * ctl, int write, struct file *file,
316 void *buffer, size_t * len)
317 {
318 int retval = 0, i;
319 unsigned long val, pll;
320 #define TMPBUFLEN 64
321 #define MAX_CPU_FREQ 396
322 char buf[TMPBUFLEN], *p;
323 unsigned long flags, intc0_mask, intc1_mask;
324 unsigned long old_baud_base, old_cpu_freq, baud_rate, old_clk,
325 old_refresh;
326 unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh;
327
328 spin_lock_irqsave(&pm_lock, flags);
329 if (!write) {
330 *len = 0;
331 } else {
332 /* Parse the new frequency */
333 if (*len > TMPBUFLEN - 1) {
334 spin_unlock_irqrestore(&pm_lock, flags);
335 return -EFAULT;
336 }
337 if (copy_from_user(buf, buffer, *len)) {
338 spin_unlock_irqrestore(&pm_lock, flags);
339 return -EFAULT;
340 }
341 buf[*len] = 0;
342 p = buf;
343 val = simple_strtoul(p, &p, 0);
344 if (val > MAX_CPU_FREQ) {
345 spin_unlock_irqrestore(&pm_lock, flags);
346 return -EFAULT;
347 }
348
349 pll = val / 12;
350 if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */
351 /* revisit this for higher speed cpus */
352 spin_unlock_irqrestore(&pm_lock, flags);
353 return -EFAULT;
354 }
355
356 old_baud_base = get_au1x00_uart_baud_base();
357 old_cpu_freq = get_au1x00_speed();
358
359 new_cpu_freq = pll * 12 * 1000000;
360 new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
361 set_au1x00_speed(new_cpu_freq);
362 set_au1x00_uart_baud_base(new_baud_base);
363
364 old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff;
365 new_refresh =
366 ((old_refresh * new_cpu_freq) /
367 old_cpu_freq) | (au_readl(MEM_SDREFCFG) & ~0x1ffffff);
368
369 au_writel(pll, SYS_CPUPLL);
370 au_sync_delay(1);
371 au_writel(new_refresh, MEM_SDREFCFG);
372 au_sync_delay(1);
373
374 for (i = 0; i < 4; i++) {
375 if (au_readl
376 (UART_BASE + UART_MOD_CNTRL +
377 i * 0x00100000) == 3) {
378 old_clk =
379 au_readl(UART_BASE + UART_CLK +
380 i * 0x00100000);
381 // baud_rate = baud_base/clk
382 baud_rate = old_baud_base / old_clk;
383 /* we won't get an exact baud rate and the error
384 * could be significant enough that our new
385 * calculation will result in a clock that will
386 * give us a baud rate that's too far off from
387 * what we really want.
388 */
389 if (baud_rate > 100000)
390 baud_rate = 115200;
391 else if (baud_rate > 50000)
392 baud_rate = 57600;
393 else if (baud_rate > 30000)
394 baud_rate = 38400;
395 else if (baud_rate > 17000)
396 baud_rate = 19200;
397 else
398 (baud_rate = 9600);
399 // new_clk = new_baud_base/baud_rate
400 new_clk = new_baud_base / baud_rate;
401 au_writel(new_clk,
402 UART_BASE + UART_CLK +
403 i * 0x00100000);
404 au_sync_delay(10);
405 }
406 }
407 }
408
409
410 /* We don't want _any_ interrupts other than
411 * match20. Otherwise our calibrate_delay()
412 * calculation will be off, potentially a lot.
413 */
414 intc0_mask = save_local_and_disable(0);
415 intc1_mask = save_local_and_disable(1);
416 local_enable_irq(AU1000_TOY_MATCH2_INT);
417 spin_unlock_irqrestore(&pm_lock, flags);
418 calibrate_delay();
419 restore_local_and_enable(0, intc0_mask);
420 restore_local_and_enable(1, intc1_mask);
421 return retval;
422 }
423
424
425 static struct ctl_table pm_table[] = {
426 {ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, &pm_do_suspend},
427 {ACPI_SLEEP, "sleep", NULL, 0, 0600, NULL, &pm_do_sleep},
428 {CTL_ACPI, "freq", NULL, 0, 0600, NULL, &pm_do_freq},
429 {0}
430 };
431
432 static struct ctl_table pm_dir_table[] = {
433 {CTL_ACPI, "pm", NULL, 0, 0555, pm_table},
434 {0}
435 };
436
437 /*
438 * Initialize power interface
439 */
pm_init(void)440 static int __init pm_init(void)
441 {
442 register_sysctl_table(pm_dir_table, 1);
443 return 0;
444 }
445
446 __initcall(pm_init);
447
448
449 /*
450 * This is right out of init/main.c
451 */
452
453 /* This is the number of bits of precision for the loops_per_jiffy. Each
454 bit takes on average 1.5/HZ seconds. This (like the original) is a little
455 better than 1% */
456 #define LPS_PREC 8
457
calibrate_delay(void)458 static void calibrate_delay(void)
459 {
460 unsigned long ticks, loopbit;
461 int lps_precision = LPS_PREC;
462
463 loops_per_jiffy = (1 << 12);
464
465 while (loops_per_jiffy <<= 1) {
466 /* wait for "start of" clock tick */
467 ticks = jiffies;
468 while (ticks == jiffies)
469 /* nothing */ ;
470 /* Go .. */
471 ticks = jiffies;
472 __delay(loops_per_jiffy);
473 ticks = jiffies - ticks;
474 if (ticks)
475 break;
476 }
477
478 /* Do a binary approximation to get loops_per_jiffy set to equal one clock
479 (up to lps_precision bits) */
480 loops_per_jiffy >>= 1;
481 loopbit = loops_per_jiffy;
482 while (lps_precision-- && (loopbit >>= 1)) {
483 loops_per_jiffy |= loopbit;
484 ticks = jiffies;
485 while (ticks == jiffies);
486 ticks = jiffies;
487 __delay(loops_per_jiffy);
488 if (jiffies != ticks) /* longer than 1 tick */
489 loops_per_jiffy &= ~loopbit;
490 }
491 }
492 #endif /* CONFIG_PM */
493