1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/sched.h>
29 #include <linux/config.h>
30 #include <linux/smp_lock.h>
31 #include <linux/mc146818rtc.h>
32 #include <linux/acpi.h>
33
34 #include <asm/io.h>
35 #include <asm/smp.h>
36 #include <asm/desc.h>
37 #include <asm/smpboot.h>
38
39 #undef APIC_LOCKUP_DEBUG
40
41 #define APIC_LOCKUP_DEBUG
42
43 static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED;
44
45 unsigned int int_dest_addr_mode = APIC_DEST_LOGICAL;
46 unsigned char int_delivery_mode = dest_LowestPrio;
47
48
49 /*
50 * # of IRQ routing registers
51 */
52 int nr_ioapic_registers[MAX_IO_APICS];
53
54 /*
55 * Rough estimation of how many shared IRQs there are, can
56 * be changed anytime.
57 */
58 #define MAX_PLUS_SHARED_IRQS NR_IRQS
59 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
60
61 /*
62 * This is performance-critical, we want to do it O(1)
63 *
64 * the indexing order of this array favors 1:1 mappings
65 * between pins and IRQs.
66 */
67
68 static struct irq_pin_list {
69 int apic, pin, next;
70 } irq_2_pin[PIN_MAP_SIZE];
71
72 /*
73 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
74 * shared ISA-space IRQs, so we have to support them. We are super
75 * fast in the common case, and fast for shared ISA-space IRQs.
76 */
add_pin_to_irq(unsigned int irq,int apic,int pin)77 static void __init add_pin_to_irq(unsigned int irq, int apic, int pin)
78 {
79 static int first_free_entry = NR_IRQS;
80 struct irq_pin_list *entry = irq_2_pin + irq;
81
82 while (entry->next)
83 entry = irq_2_pin + entry->next;
84
85 if (entry->pin != -1) {
86 entry->next = first_free_entry;
87 entry = irq_2_pin + entry->next;
88 if (++first_free_entry >= PIN_MAP_SIZE)
89 panic("io_apic.c: whoops");
90 }
91 entry->apic = apic;
92 entry->pin = pin;
93 }
94
95 /*
96 * Reroute an IRQ to a different pin.
97 */
replace_pin_at_irq(unsigned int irq,int oldapic,int oldpin,int newapic,int newpin)98 static void __init replace_pin_at_irq(unsigned int irq,
99 int oldapic, int oldpin,
100 int newapic, int newpin)
101 {
102 struct irq_pin_list *entry = irq_2_pin + irq;
103
104 while (1) {
105 if (entry->apic == oldapic && entry->pin == oldpin) {
106 entry->apic = newapic;
107 entry->pin = newpin;
108 }
109 if (!entry->next)
110 break;
111 entry = irq_2_pin + entry->next;
112 }
113 }
114
115 #define __DO_ACTION(R, ACTION, FINAL) \
116 \
117 { \
118 int pin; \
119 struct irq_pin_list *entry = irq_2_pin + irq; \
120 \
121 for (;;) { \
122 unsigned int reg; \
123 pin = entry->pin; \
124 if (pin == -1) \
125 break; \
126 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
127 reg ACTION; \
128 io_apic_write(entry->apic, 0x10 + R + pin*2, reg); \
129 if (!entry->next) \
130 break; \
131 entry = irq_2_pin + entry->next; \
132 } \
133 FINAL; \
134 }
135
136 #define DO_ACTION(name,R,ACTION, FINAL) \
137 \
138 static void name##_IO_APIC_irq (unsigned int irq) \
139 __DO_ACTION(R, ACTION, FINAL)
140
141 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
142 /* mask = 1 */
143 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
144 /* mask = 0 */
145 DO_ACTION( __mask_and_edge, 0, = (reg & 0xffff7fff) | 0x00010000, )
146 /* mask = 1, trigger = 0 */
147 DO_ACTION( __unmask_and_level, 0, = (reg & 0xfffeffff) | 0x00008000, )
148 /* mask = 0, trigger = 1 */
149
mask_IO_APIC_irq(unsigned int irq)150 static void mask_IO_APIC_irq (unsigned int irq)
151 {
152 unsigned long flags;
153
154 spin_lock_irqsave(&ioapic_lock, flags);
155 __mask_IO_APIC_irq(irq);
156 spin_unlock_irqrestore(&ioapic_lock, flags);
157 }
158
unmask_IO_APIC_irq(unsigned int irq)159 static void unmask_IO_APIC_irq (unsigned int irq)
160 {
161 unsigned long flags;
162
163 spin_lock_irqsave(&ioapic_lock, flags);
164 __unmask_IO_APIC_irq(irq);
165 spin_unlock_irqrestore(&ioapic_lock, flags);
166 }
167
clear_IO_APIC_pin(unsigned int apic,unsigned int pin)168 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
169 {
170 struct IO_APIC_route_entry entry;
171 unsigned long flags;
172
173 /* Check delivery_mode to be sure we're not clearing an SMI pin */
174 spin_lock_irqsave(&ioapic_lock, flags);
175 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
176 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
177 spin_unlock_irqrestore(&ioapic_lock, flags);
178 if (entry.delivery_mode == dest_SMI)
179 return;
180
181 /*
182 * Disable it in the IO-APIC irq-routing table:
183 */
184 memset(&entry, 0, sizeof(entry));
185 entry.mask = 1;
186 spin_lock_irqsave(&ioapic_lock, flags);
187 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
188 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
189 spin_unlock_irqrestore(&ioapic_lock, flags);
190 }
191
clear_IO_APIC(void)192 static void clear_IO_APIC (void)
193 {
194 int apic, pin;
195
196 for (apic = 0; apic < nr_ioapics; apic++)
197 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
198 clear_IO_APIC_pin(apic, pin);
199 }
200
201 /*
202 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
203 * specific CPU-side IRQs.
204 */
205
206 #define MAX_PIRQS 8
207 int pirq_entries [MAX_PIRQS];
208 int pirqs_enabled;
209 int skip_ioapic_setup;
210
noioapic_setup(char * str)211 static int __init noioapic_setup(char *str)
212 {
213 skip_ioapic_setup = 1;
214 return 1;
215 }
216
217 __setup("noapic", noioapic_setup);
218
ioapic_setup(char * str)219 static int __init ioapic_setup(char *str)
220 {
221 skip_ioapic_setup = 0;
222 return 1;
223 }
224
225 __setup("apic", ioapic_setup);
226
ioapic_pirq_setup(char * str)227 static int __init ioapic_pirq_setup(char *str)
228 {
229 int i, max;
230 int ints[MAX_PIRQS+1];
231
232 get_options(str, ARRAY_SIZE(ints), ints);
233
234 for (i = 0; i < MAX_PIRQS; i++)
235 pirq_entries[i] = -1;
236
237 pirqs_enabled = 1;
238 printk(KERN_INFO "PIRQ redirection, working around broken MP-BIOS.\n");
239 max = MAX_PIRQS;
240 if (ints[0] < MAX_PIRQS)
241 max = ints[0];
242
243 for (i = 0; i < max; i++) {
244 printk(KERN_DEBUG "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
245 /*
246 * PIRQs are mapped upside down, usually.
247 */
248 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
249 }
250 return 1;
251 }
252
253 __setup("pirq=", ioapic_pirq_setup);
254
255 /*
256 * Find the IRQ entry number of a certain pin.
257 */
find_irq_entry(int apic,int pin,int type)258 static int __init find_irq_entry(int apic, int pin, int type)
259 {
260 int i;
261
262 for (i = 0; i < mp_irq_entries; i++)
263 if (mp_irqs[i].mpc_irqtype == type &&
264 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
265 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
266 mp_irqs[i].mpc_dstirq == pin)
267 return i;
268
269 return -1;
270 }
271
272 /*
273 * Find the pin to which IRQ[irq] (ISA) is connected
274 */
find_isa_irq_pin(int irq,int type)275 static int __init find_isa_irq_pin(int irq, int type)
276 {
277 int i;
278
279 for (i = 0; i < mp_irq_entries; i++) {
280 int lbus = mp_irqs[i].mpc_srcbus;
281
282 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
283 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
284 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
285 (mp_irqs[i].mpc_irqtype == type) &&
286 (mp_irqs[i].mpc_srcbusirq == irq))
287
288 return mp_irqs[i].mpc_dstirq;
289 }
290 return -1;
291 }
292
293 /*
294 * Find a specific PCI IRQ entry.
295 * Not an __init, possibly needed by modules
296 */
297 static int pin_2_irq(int idx, int apic, int pin);
298
IO_APIC_get_PCI_irq_vector(int bus,int slot,int pin)299 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
300 {
301 int apic, i, best_guess = -1;
302
303 Dprintk("querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
304 bus, slot, pin);
305 if ((mp_bus_id_to_pci_bus==NULL) || (mp_bus_id_to_pci_bus[bus] == -1)) {
306 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
307 return -1;
308 }
309 for (i = 0; i < mp_irq_entries; i++) {
310 int lbus = mp_irqs[i].mpc_srcbus;
311
312 for (apic = 0; apic < nr_ioapics; apic++)
313 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
314 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
315 break;
316
317 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
318 !mp_irqs[i].mpc_irqtype &&
319 (bus == lbus) &&
320 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
321 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
322
323 if (!(apic || IO_APIC_IRQ(irq)))
324 continue;
325
326 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
327 return irq;
328 /*
329 * Use the first all-but-pin matching entry as a
330 * best-guess fuzzy result for broken mptables.
331 */
332 if (best_guess < 0)
333 best_guess = irq;
334 }
335 }
336 return best_guess;
337 }
338
339 /*
340 * EISA Edge/Level control register, ELCR
341 */
EISA_ELCR(unsigned int irq)342 static int __init EISA_ELCR(unsigned int irq)
343 {
344 if (irq < 16) {
345 unsigned int port = 0x4d0 + (irq >> 3);
346 return (inb(port) >> (irq & 7)) & 1;
347 }
348 printk(KERN_INFO "Broken MPtable reports ISA irq %d\n", irq);
349 return 0;
350 }
351
352 /* EISA interrupts are always polarity zero and can be edge or level
353 * trigger depending on the ELCR value. If an interrupt is listed as
354 * EISA conforming in the MP table, that means its trigger type must
355 * be read in from the ELCR */
356
357 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
358 #define default_EISA_polarity(idx) (0)
359
360 /* ISA interrupts are always polarity zero edge triggered,
361 * when listed as conforming in the MP table. */
362
363 #define default_ISA_trigger(idx) (0)
364 #define default_ISA_polarity(idx) (0)
365
366 /* PCI interrupts are always polarity one level triggered,
367 * when listed as conforming in the MP table. */
368
369 #define default_PCI_trigger(idx) (1)
370 #define default_PCI_polarity(idx) (1)
371
372 /* MCA interrupts are always polarity zero level triggered,
373 * when listed as conforming in the MP table. */
374
375 #define default_MCA_trigger(idx) (1)
376 #define default_MCA_polarity(idx) (0)
377
MPBIOS_polarity(int idx)378 static int __init MPBIOS_polarity(int idx)
379 {
380 int bus = mp_irqs[idx].mpc_srcbus;
381 int polarity;
382
383 /*
384 * Determine IRQ line polarity (high active or low active):
385 */
386 switch (mp_irqs[idx].mpc_irqflag & 3)
387 {
388 case 0: /* conforms, ie. bus-type dependent polarity */
389 {
390 switch (mp_bus_id_to_type[bus])
391 {
392 case MP_BUS_ISA: /* ISA pin */
393 {
394 polarity = default_ISA_polarity(idx);
395 break;
396 }
397 case MP_BUS_EISA: /* EISA pin */
398 {
399 polarity = default_EISA_polarity(idx);
400 break;
401 }
402 case MP_BUS_PCI: /* PCI pin */
403 {
404 polarity = default_PCI_polarity(idx);
405 break;
406 }
407 case MP_BUS_MCA: /* MCA pin */
408 {
409 polarity = default_MCA_polarity(idx);
410 break;
411 }
412 default:
413 {
414 printk(KERN_WARNING "broken BIOS!!\n");
415 polarity = 1;
416 break;
417 }
418 }
419 break;
420 }
421 case 1: /* high active */
422 {
423 polarity = 0;
424 break;
425 }
426 case 2: /* reserved */
427 {
428 printk(KERN_WARNING "broken BIOS!!\n");
429 polarity = 1;
430 break;
431 }
432 case 3: /* low active */
433 {
434 polarity = 1;
435 break;
436 }
437 default: /* invalid */
438 {
439 printk(KERN_WARNING "broken BIOS!!\n");
440 polarity = 1;
441 break;
442 }
443 }
444 return polarity;
445 }
446
MPBIOS_trigger(int idx)447 static int __init MPBIOS_trigger(int idx)
448 {
449 int bus = mp_irqs[idx].mpc_srcbus;
450 int trigger;
451
452 /*
453 * Determine IRQ trigger mode (edge or level sensitive):
454 */
455 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
456 {
457 case 0: /* conforms, ie. bus-type dependent */
458 {
459 switch (mp_bus_id_to_type[bus])
460 {
461 case MP_BUS_ISA: /* ISA pin */
462 {
463 trigger = default_ISA_trigger(idx);
464 break;
465 }
466 case MP_BUS_EISA: /* EISA pin */
467 {
468 trigger = default_EISA_trigger(idx);
469 break;
470 }
471 case MP_BUS_PCI: /* PCI pin */
472 {
473 trigger = default_PCI_trigger(idx);
474 break;
475 }
476 case MP_BUS_MCA: /* MCA pin */
477 {
478 trigger = default_MCA_trigger(idx);
479 break;
480 }
481 default:
482 {
483 printk(KERN_WARNING "broken BIOS!!\n");
484 trigger = 1;
485 break;
486 }
487 }
488 break;
489 }
490 case 1: /* edge */
491 {
492 trigger = 0;
493 break;
494 }
495 case 2: /* reserved */
496 {
497 printk(KERN_WARNING "broken BIOS!!\n");
498 trigger = 1;
499 break;
500 }
501 case 3: /* level */
502 {
503 trigger = 1;
504 break;
505 }
506 default: /* invalid */
507 {
508 printk(KERN_WARNING "broken BIOS!!\n");
509 trigger = 0;
510 break;
511 }
512 }
513 return trigger;
514 }
515
irq_polarity(int idx)516 static inline int irq_polarity(int idx)
517 {
518 return MPBIOS_polarity(idx);
519 }
520
irq_trigger(int idx)521 static inline int irq_trigger(int idx)
522 {
523 return MPBIOS_trigger(idx);
524 }
525
pin_2_irq(int idx,int apic,int pin)526 static int pin_2_irq(int idx, int apic, int pin)
527 {
528 int irq, i;
529 int bus = mp_irqs[idx].mpc_srcbus;
530
531 /*
532 * Debugging check, we are in big trouble if this message pops up!
533 */
534 if (mp_irqs[idx].mpc_dstirq != pin)
535 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
536
537 switch (mp_bus_id_to_type[bus])
538 {
539 case MP_BUS_ISA: /* ISA pin */
540 case MP_BUS_EISA:
541 case MP_BUS_MCA:
542 {
543 irq = mp_irqs[idx].mpc_srcbusirq;
544 break;
545 }
546 case MP_BUS_PCI: /* PCI pin */
547 {
548 /*
549 * PCI IRQs are mapped in order
550 */
551 i = irq = 0;
552 while (i < apic)
553 irq += nr_ioapic_registers[i++];
554 irq += pin;
555 break;
556 }
557 default:
558 {
559 printk(KERN_ERR "unknown bus type %d.\n",bus);
560 irq = 0;
561 break;
562 }
563 }
564
565 /*
566 * PCI IRQ command line redirection. Yes, limits are hardcoded.
567 */
568 if ((pin >= 16) && (pin <= 23)) {
569 if (pirq_entries[pin-16] != -1) {
570 if (!pirq_entries[pin-16]) {
571 printk(KERN_DEBUG "disabling PIRQ%d\n", pin-16);
572 } else {
573 irq = pirq_entries[pin-16];
574 printk(KERN_DEBUG "using PIRQ%d -> IRQ %d\n",
575 pin-16, irq);
576 }
577 }
578 }
579 return irq;
580 }
581
IO_APIC_irq_trigger(int irq)582 static inline int IO_APIC_irq_trigger(int irq)
583 {
584 int apic, idx, pin;
585
586 for (apic = 0; apic < nr_ioapics; apic++) {
587 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
588 idx = find_irq_entry(apic,pin,mp_INT);
589 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
590 return irq_trigger(idx);
591 }
592 }
593 /*
594 * nonexistent IRQs are edge default
595 */
596 return 0;
597 }
598
599 int irq_vector[NR_IRQS] = { FIRST_DEVICE_VECTOR , 0 };
600
assign_irq_vector(int irq)601 static int __init assign_irq_vector(int irq)
602 {
603 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
604 if (IO_APIC_VECTOR(irq) > 0)
605 return IO_APIC_VECTOR(irq);
606 next:
607 current_vector += 8;
608 if (current_vector == SYSCALL_VECTOR)
609 goto next;
610
611 if (current_vector > FIRST_SYSTEM_VECTOR) {
612 offset++;
613 current_vector = FIRST_DEVICE_VECTOR + offset;
614 }
615
616 if (current_vector == FIRST_SYSTEM_VECTOR)
617 panic("ran out of interrupt sources!");
618
619 IO_APIC_VECTOR(irq) = current_vector;
620 return current_vector;
621 }
622
623 extern void (*interrupt[NR_IRQS])(void);
624 static struct hw_interrupt_type ioapic_level_irq_type;
625 static struct hw_interrupt_type ioapic_edge_irq_type;
626
setup_IO_APIC_irqs(void)627 void __init setup_IO_APIC_irqs(void)
628 {
629 struct IO_APIC_route_entry entry;
630 int apic, pin, idx, irq, first_notcon = 1, vector;
631 unsigned long flags;
632
633 printk(KERN_DEBUG "init IO_APIC IRQs\n");
634
635 for (apic = 0; apic < nr_ioapics; apic++) {
636 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
637
638 /*
639 * add it to the IO-APIC irq-routing table:
640 */
641 memset(&entry,0,sizeof(entry));
642
643 entry.delivery_mode = INT_DELIVERY_MODE;
644 entry.dest_mode = (INT_DEST_ADDR_MODE != 0);
645 entry.mask = 0; /* enable IRQ */
646 entry.dest.logical.logical_dest = target_cpus();
647
648 idx = find_irq_entry(apic,pin,mp_INT);
649 if (idx == -1) {
650 if (first_notcon) {
651 printk(KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
652 first_notcon = 0;
653 } else
654 printk(", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
655 continue;
656 }
657
658 entry.trigger = irq_trigger(idx);
659 entry.polarity = irq_polarity(idx);
660
661 if (irq_trigger(idx)) {
662 entry.trigger = 1;
663 entry.mask = 1;
664 }
665
666 irq = pin_2_irq(idx, apic, pin);
667 /*
668 * skip adding the timer int on secondary nodes, which causes
669 * a small but painful rift in the time-space continuum
670 */
671 if ((clustered_apic_mode == CLUSTERED_APIC_NUMAQ)
672 && (apic != 0) && (irq == 0))
673 continue;
674 else
675 add_pin_to_irq(irq, apic, pin);
676
677 if (!apic && !IO_APIC_IRQ(irq))
678 continue;
679
680 if (IO_APIC_IRQ(irq)) {
681 vector = assign_irq_vector(irq);
682 entry.vector = vector;
683
684 if (IO_APIC_irq_trigger(irq))
685 irq_desc[irq].handler = &ioapic_level_irq_type;
686 else
687 irq_desc[irq].handler = &ioapic_edge_irq_type;
688
689 set_intr_gate(vector, interrupt[irq]);
690
691 if (!apic && (irq < 16))
692 disable_8259A_irq(irq);
693 }
694 spin_lock_irqsave(&ioapic_lock, flags);
695 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
696 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
697 spin_unlock_irqrestore(&ioapic_lock, flags);
698 }
699 }
700
701 if (!first_notcon)
702 printk(" not connected.\n");
703 }
704
705 /*
706 * Set up the 8259A-master output pin as broadcast to all
707 * CPUs.
708 */
setup_ExtINT_IRQ0_pin(unsigned int pin,int vector)709 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
710 {
711 struct IO_APIC_route_entry entry;
712 unsigned long flags;
713
714 memset(&entry,0,sizeof(entry));
715
716 disable_8259A_irq(0);
717
718 /* mask LVT0 */
719 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
720
721 /*
722 * We use logical delivery to get the timer IRQ
723 * to the first CPU.
724 */
725 entry.dest_mode = (INT_DEST_ADDR_MODE != 0);
726 entry.mask = 0; /* unmask IRQ now */
727 entry.dest.logical.logical_dest = target_cpus();
728 entry.delivery_mode = INT_DELIVERY_MODE;
729 entry.polarity = 0;
730 entry.trigger = 0;
731 entry.vector = vector;
732
733 /*
734 * The timer IRQ doesn't have to know that behind the
735 * scene we have a 8259A-master in AEOI mode ...
736 */
737 irq_desc[0].handler = &ioapic_edge_irq_type;
738
739 /*
740 * Add it to the IO-APIC irq-routing table:
741 */
742 spin_lock_irqsave(&ioapic_lock, flags);
743 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
744 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
745 spin_unlock_irqrestore(&ioapic_lock, flags);
746
747 enable_8259A_irq(0);
748 }
749
UNEXPECTED_IO_APIC(void)750 void __init UNEXPECTED_IO_APIC(void)
751 {
752 printk(KERN_WARNING
753 "An unexpected IO-APIC was found. If this kernel release is less than\n"
754 "three months old please report this to linux-smp@vger.kernel.org\n");
755 }
756
print_IO_APIC(void)757 void __init print_IO_APIC(void)
758 {
759 int apic, i;
760 struct IO_APIC_reg_00 reg_00;
761 struct IO_APIC_reg_01 reg_01;
762 struct IO_APIC_reg_02 reg_02;
763 struct IO_APIC_reg_03 reg_03;
764 unsigned long flags;
765
766 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
767 for (i = 0; i < nr_ioapics; i++)
768 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
769 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
770
771 /*
772 * We are a bit conservative about what we expect. We have to
773 * know about every hardware change ASAP.
774 */
775 printk(KERN_INFO "testing the IO APIC.......................\n");
776
777 for (apic = 0; apic < nr_ioapics; apic++) {
778
779 spin_lock_irqsave(&ioapic_lock, flags);
780 *(int *)®_00 = io_apic_read(apic, 0);
781 *(int *)®_01 = io_apic_read(apic, 1);
782 if (reg_01.version >= 0x10)
783 *(int *)®_02 = io_apic_read(apic, 2);
784 if (reg_01.version >= 0x20)
785 *(int *)®_03 = io_apic_read(apic, 3);
786 spin_unlock_irqrestore(&ioapic_lock, flags);
787
788 printk("\n");
789 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
790 printk(KERN_DEBUG ".... register #00: %08X\n", *(int *)®_00);
791 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.ID);
792 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.delivery_type);
793 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.LTS);
794 if (reg_00.__reserved_0 || reg_00.__reserved_1 || reg_00.__reserved_2)
795 UNEXPECTED_IO_APIC();
796
797 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
798 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.entries);
799 if ( (reg_01.entries != 0x0f) && /* older (Neptune) boards */
800 (reg_01.entries != 0x17) && /* typical ISA+PCI boards */
801 (reg_01.entries != 0x1b) && /* Compaq Proliant boards */
802 (reg_01.entries != 0x1f) && /* dual Xeon boards */
803 (reg_01.entries != 0x22) && /* bigger Xeon boards */
804 (reg_01.entries != 0x2E) &&
805 (reg_01.entries != 0x3F)
806 )
807 UNEXPECTED_IO_APIC();
808
809 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.PRQ);
810 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.version);
811 if ( (reg_01.version != 0x01) && /* 82489DX IO-APICs */
812 (reg_01.version != 0x02) && /* VIA */
813 (reg_01.version != 0x03) && /* later VIA */
814 (reg_01.version != 0x10) && /* oldest IO-APICs */
815 (reg_01.version != 0x11) && /* Pentium/Pro IO-APICs */
816 (reg_01.version != 0x13) && /* Xeon IO-APICs */
817 (reg_01.version != 0x20) /* Intel P64H (82806 AA) */
818 )
819 UNEXPECTED_IO_APIC();
820 if (reg_01.__reserved_1 || reg_01.__reserved_2)
821 UNEXPECTED_IO_APIC();
822
823 /*
824 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
825 * but the value of reg_02 is read as the previous read register
826 * value, so ignore it if reg_02 == reg_01.
827 */
828 if (reg_01.version >= 0x10 && *(int *)®_02 != *(int *)®_01) {
829 printk(KERN_DEBUG ".... register #02: %08X\n", *(int *)®_02);
830 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.arbitration);
831 if (reg_02.__reserved_1 || reg_02.__reserved_2)
832 UNEXPECTED_IO_APIC();
833 }
834
835 /*
836 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
837 * or reg_03, but the value of reg_0[23] is read as the previous read
838 * register value, so ignore it if reg_03 == reg_0[12].
839 */
840 if (reg_01.version >= 0x20 && *(int *)®_03 != *(int *)®_02 &&
841 *(int *)®_03 != *(int *)®_01) {
842 printk(KERN_DEBUG ".... register #03: %08X\n", *(int *)®_03);
843 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.boot_DT);
844 if (reg_03.__reserved_1)
845 UNEXPECTED_IO_APIC();
846 }
847
848 printk(KERN_DEBUG ".... IRQ redirection table:\n");
849
850 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
851 " Stat Dest Deli Vect: \n");
852
853 for (i = 0; i <= reg_01.entries; i++) {
854 struct IO_APIC_route_entry entry;
855
856 spin_lock_irqsave(&ioapic_lock, flags);
857 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
858 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
859 spin_unlock_irqrestore(&ioapic_lock, flags);
860
861 printk(KERN_DEBUG " %02x %03X %02X ",
862 i,
863 entry.dest.logical.logical_dest,
864 entry.dest.physical.physical_dest
865 );
866
867 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
868 entry.mask,
869 entry.trigger,
870 entry.irr,
871 entry.polarity,
872 entry.delivery_status,
873 entry.dest_mode,
874 entry.delivery_mode,
875 entry.vector
876 );
877 }
878 }
879 printk(KERN_DEBUG "IRQ to pin mappings:\n");
880 for (i = 0; i < NR_IRQS; i++) {
881 struct irq_pin_list *entry = irq_2_pin + i;
882 if (entry->pin < 0)
883 continue;
884 printk(KERN_DEBUG "IRQ%d ", i);
885 for (;;) {
886 printk("-> %d:%d", entry->apic, entry->pin);
887 if (!entry->next)
888 break;
889 entry = irq_2_pin + entry->next;
890 }
891 printk("\n");
892 }
893
894 printk(KERN_INFO ".................................... done.\n");
895
896 return;
897 }
898
print_APIC_bitfield(int base)899 static void print_APIC_bitfield (int base)
900 {
901 unsigned int v;
902 int i, j;
903
904 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
905 for (i = 0; i < 8; i++) {
906 v = apic_read(base + i*0x10);
907 for (j = 0; j < 32; j++) {
908 if (v & (1<<j))
909 printk("1");
910 else
911 printk("0");
912 }
913 printk("\n");
914 }
915 }
916
print_local_APIC(void * dummy)917 void /*__init*/ print_local_APIC(void * dummy)
918 {
919 unsigned int v, ver, maxlvt;
920
921 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
922 smp_processor_id(), hard_smp_processor_id());
923 v = apic_read(APIC_ID);
924 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
925 v = apic_read(APIC_LVR);
926 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
927 ver = GET_APIC_VERSION(v);
928 maxlvt = get_maxlvt();
929
930 v = apic_read(APIC_TASKPRI);
931 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
932
933 if (APIC_INTEGRATED(ver)) { /* !82489DX */
934 v = apic_read(APIC_ARBPRI);
935 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
936 v & APIC_ARBPRI_MASK);
937 v = apic_read(APIC_PROCPRI);
938 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
939 }
940
941 v = apic_read(APIC_EOI);
942 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
943 v = apic_read(APIC_RRR);
944 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
945 v = apic_read(APIC_LDR);
946 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
947 v = apic_read(APIC_DFR);
948 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
949 v = apic_read(APIC_SPIV);
950 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
951
952 printk(KERN_DEBUG "... APIC ISR field:\n");
953 print_APIC_bitfield(APIC_ISR);
954 printk(KERN_DEBUG "... APIC TMR field:\n");
955 print_APIC_bitfield(APIC_TMR);
956 printk(KERN_DEBUG "... APIC IRR field:\n");
957 print_APIC_bitfield(APIC_IRR);
958
959 if (APIC_INTEGRATED(ver)) { /* !82489DX */
960 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
961 apic_write(APIC_ESR, 0);
962 v = apic_read(APIC_ESR);
963 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
964 }
965
966 v = apic_read(APIC_ICR);
967 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
968 v = apic_read(APIC_ICR2);
969 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
970
971 v = apic_read(APIC_LVTT);
972 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
973
974 if (maxlvt > 3) { /* PC is LVT#4. */
975 v = apic_read(APIC_LVTPC);
976 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
977 }
978 v = apic_read(APIC_LVT0);
979 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
980 v = apic_read(APIC_LVT1);
981 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
982
983 if (maxlvt > 2) { /* ERR is LVT#3. */
984 v = apic_read(APIC_LVTERR);
985 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
986 }
987
988 v = apic_read(APIC_TMICT);
989 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
990 v = apic_read(APIC_TMCCT);
991 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
992 v = apic_read(APIC_TDCR);
993 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
994 printk("\n");
995 }
996
print_all_local_APICs(void)997 void print_all_local_APICs (void)
998 {
999 smp_call_function(print_local_APIC, NULL, 1, 1);
1000 print_local_APIC(NULL);
1001 }
1002
print_PIC(void)1003 void /*__init*/ print_PIC(void)
1004 {
1005 extern spinlock_t i8259A_lock;
1006 unsigned int v, flags;
1007
1008 printk(KERN_DEBUG "\nprinting PIC contents\n");
1009
1010 spin_lock_irqsave(&i8259A_lock, flags);
1011
1012 v = inb(0xa1) << 8 | inb(0x21);
1013 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1014
1015 v = inb(0xa0) << 8 | inb(0x20);
1016 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1017
1018 outb(0x0b,0xa0);
1019 outb(0x0b,0x20);
1020 v = inb(0xa0) << 8 | inb(0x20);
1021 outb(0x0a,0xa0);
1022 outb(0x0a,0x20);
1023
1024 spin_unlock_irqrestore(&i8259A_lock, flags);
1025
1026 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1027
1028 v = inb(0x4d1) << 8 | inb(0x4d0);
1029 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1030 }
1031
enable_IO_APIC(void)1032 static void __init enable_IO_APIC(void)
1033 {
1034 struct IO_APIC_reg_01 reg_01;
1035 int i;
1036 unsigned long flags;
1037
1038 for (i = 0; i < PIN_MAP_SIZE; i++) {
1039 irq_2_pin[i].pin = -1;
1040 irq_2_pin[i].next = 0;
1041 }
1042 if (!pirqs_enabled)
1043 for (i = 0; i < MAX_PIRQS; i++)
1044 pirq_entries[i] = -1;
1045
1046 /*
1047 * The number of IO-APIC IRQ registers (== #pins):
1048 */
1049 for (i = 0; i < nr_ioapics; i++) {
1050 spin_lock_irqsave(&ioapic_lock, flags);
1051 *(int *)®_01 = io_apic_read(i, 1);
1052 spin_unlock_irqrestore(&ioapic_lock, flags);
1053 nr_ioapic_registers[i] = reg_01.entries+1;
1054 }
1055
1056 /*
1057 * Do not trust the IO-APIC being empty at bootup
1058 */
1059 clear_IO_APIC();
1060 }
1061
1062 /*
1063 * Not an __init, needed by the reboot code
1064 */
disable_IO_APIC(void)1065 void disable_IO_APIC(void)
1066 {
1067 /*
1068 * Clear the IO-APIC before rebooting:
1069 */
1070 clear_IO_APIC();
1071
1072 disconnect_bsp_APIC();
1073 }
1074
1075 /*
1076 * function to set the IO-APIC physical IDs based on the
1077 * values stored in the MPC table.
1078 *
1079 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1080 */
1081
setup_ioapic_ids_from_mpc(void)1082 static void __init setup_ioapic_ids_from_mpc (void)
1083 {
1084 struct IO_APIC_reg_00 reg_00;
1085 unsigned long phys_id_present_map = phys_cpu_present_map;
1086 int apic;
1087 int i;
1088 unsigned char old_id;
1089 unsigned long flags;
1090
1091 if (clustered_apic_mode)
1092 /* We don't have a good way to do this yet - hack */
1093 phys_id_present_map = (u_long) 0xf;
1094 /*
1095 * Set the IOAPIC ID to the value stored in the MPC table.
1096 */
1097 for (apic = 0; apic < nr_ioapics; apic++) {
1098
1099 /* Read the register 0 value */
1100 spin_lock_irqsave(&ioapic_lock, flags);
1101 *(int *)®_00 = io_apic_read(apic, 0);
1102 spin_unlock_irqrestore(&ioapic_lock, flags);
1103
1104 old_id = mp_ioapics[apic].mpc_apicid;
1105
1106 if (mp_ioapics[apic].mpc_apicid >= apic_broadcast_id) {
1107 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1108 apic, mp_ioapics[apic].mpc_apicid);
1109 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1110 reg_00.ID);
1111 mp_ioapics[apic].mpc_apicid = reg_00.ID;
1112 }
1113
1114 /*
1115 * Sanity check, is the ID really free? Every APIC in a
1116 * system must have a unique ID or we get lots of nice
1117 * 'stuck on smp_invalidate_needed IPI wait' messages.
1118 * I/O APIC IDs no longer have any meaning for xAPICs and SAPICs.
1119 */
1120 if ((clustered_apic_mode != CLUSTERED_APIC_XAPIC) &&
1121 (phys_id_present_map & (1 << mp_ioapics[apic].mpc_apicid))) {
1122 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1123 apic, mp_ioapics[apic].mpc_apicid);
1124 for (i = 0; i < 0xf; i++)
1125 if (!(phys_id_present_map & (1 << i)))
1126 break;
1127 if (i >= apic_broadcast_id)
1128 panic("Max APIC ID exceeded!\n");
1129 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1130 i);
1131 phys_id_present_map |= 1 << i;
1132 mp_ioapics[apic].mpc_apicid = i;
1133 } else {
1134 printk("Setting %d in the phys_id_present_map\n", mp_ioapics[apic].mpc_apicid);
1135 phys_id_present_map |= 1 << mp_ioapics[apic].mpc_apicid;
1136 }
1137
1138
1139 /*
1140 * We need to adjust the IRQ routing table
1141 * if the ID changed.
1142 */
1143 if (old_id != mp_ioapics[apic].mpc_apicid)
1144 for (i = 0; i < mp_irq_entries; i++)
1145 if (mp_irqs[i].mpc_dstapic == old_id)
1146 mp_irqs[i].mpc_dstapic
1147 = mp_ioapics[apic].mpc_apicid;
1148
1149 /*
1150 * Read the right value from the MPC table and
1151 * write it into the ID register.
1152 */
1153 printk(KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1154 mp_ioapics[apic].mpc_apicid);
1155
1156 reg_00.ID = mp_ioapics[apic].mpc_apicid;
1157 spin_lock_irqsave(&ioapic_lock, flags);
1158 io_apic_write(apic, 0, *(int *)®_00);
1159 spin_unlock_irqrestore(&ioapic_lock, flags);
1160
1161 /*
1162 * Sanity check
1163 */
1164 spin_lock_irqsave(&ioapic_lock, flags);
1165 *(int *)®_00 = io_apic_read(apic, 0);
1166 spin_unlock_irqrestore(&ioapic_lock, flags);
1167 if (reg_00.ID != mp_ioapics[apic].mpc_apicid)
1168 panic("could not set ID!\n");
1169 else
1170 printk(" ok.\n");
1171 }
1172 }
1173
1174 /*
1175 * There is a nasty bug in some older SMP boards, their mptable lies
1176 * about the timer IRQ. We do the following to work around the situation:
1177 *
1178 * - timer IRQ defaults to IO-APIC IRQ
1179 * - if this function detects that timer IRQs are defunct, then we fall
1180 * back to ISA timer IRQs
1181 */
timer_irq_works(void)1182 static int __init timer_irq_works(void)
1183 {
1184 unsigned int t1 = jiffies;
1185
1186 sti();
1187 /* Let ten ticks pass... */
1188 mdelay((10 * 1000) / HZ);
1189
1190 /*
1191 * Expect a few ticks at least, to be sure some possible
1192 * glue logic does not lock up after one or two first
1193 * ticks in a non-ExtINT mode. Also the local APIC
1194 * might have cached one ExtINT interrupt. Finally, at
1195 * least one tick may be lost due to delays.
1196 */
1197 if (jiffies - t1 > 4 && jiffies - t1 < 16)
1198 return 1;
1199
1200 return 0;
1201 }
1202
1203 /*
1204 * In the SMP+IOAPIC case it might happen that there are an unspecified
1205 * number of pending IRQ events unhandled. These cases are very rare,
1206 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1207 * better to do it this way as thus we do not have to be aware of
1208 * 'pending' interrupts in the IRQ path, except at this point.
1209 */
1210 /*
1211 * Edge triggered needs to resend any interrupt
1212 * that was delayed but this is now handled in the device
1213 * independent code.
1214 */
1215 #define enable_edge_ioapic_irq unmask_IO_APIC_irq
1216
disable_edge_ioapic_irq(unsigned int irq)1217 static void disable_edge_ioapic_irq (unsigned int irq) { /* nothing */ }
1218
1219 /*
1220 * Starting up a edge-triggered IO-APIC interrupt is
1221 * nasty - we need to make sure that we get the edge.
1222 * If it is already asserted for some reason, we need
1223 * return 1 to indicate that is was pending.
1224 *
1225 * This is not complete - we should be able to fake
1226 * an edge even if it isn't on the 8259A...
1227 */
1228
startup_edge_ioapic_irq(unsigned int irq)1229 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1230 {
1231 int was_pending = 0;
1232 unsigned long flags;
1233
1234 spin_lock_irqsave(&ioapic_lock, flags);
1235 if (irq < 16) {
1236 disable_8259A_irq(irq);
1237 if (i8259A_irq_pending(irq))
1238 was_pending = 1;
1239 }
1240 __unmask_IO_APIC_irq(irq);
1241 spin_unlock_irqrestore(&ioapic_lock, flags);
1242
1243 return was_pending;
1244 }
1245
1246 #define shutdown_edge_ioapic_irq disable_edge_ioapic_irq
1247
1248 /*
1249 * Once we have recorded IRQ_PENDING already, we can mask the
1250 * interrupt for real. This prevents IRQ storms from unhandled
1251 * devices.
1252 */
ack_edge_ioapic_irq(unsigned int irq)1253 static void ack_edge_ioapic_irq(unsigned int irq)
1254 {
1255 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1256 == (IRQ_PENDING | IRQ_DISABLED))
1257 mask_IO_APIC_irq(irq);
1258 ack_APIC_irq();
1259 }
1260
end_edge_ioapic_irq(unsigned int i)1261 static void end_edge_ioapic_irq (unsigned int i) { /* nothing */ }
1262
1263
1264 /*
1265 * Level triggered interrupts can just be masked,
1266 * and shutting down and starting up the interrupt
1267 * is the same as enabling and disabling them -- except
1268 * with a startup need to return a "was pending" value.
1269 *
1270 * Level triggered interrupts are special because we
1271 * do not touch any IO-APIC register while handling
1272 * them. We ack the APIC in the end-IRQ handler, not
1273 * in the start-IRQ-handler. Protection against reentrance
1274 * from the same interrupt is still provided, both by the
1275 * generic IRQ layer and by the fact that an unacked local
1276 * APIC does not accept IRQs.
1277 */
startup_level_ioapic_irq(unsigned int irq)1278 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1279 {
1280 unmask_IO_APIC_irq(irq);
1281
1282 return 0; /* don't check for pending */
1283 }
1284
1285 #define shutdown_level_ioapic_irq mask_IO_APIC_irq
1286 #define enable_level_ioapic_irq unmask_IO_APIC_irq
1287 #define disable_level_ioapic_irq mask_IO_APIC_irq
1288
end_level_ioapic_irq(unsigned int irq)1289 static void end_level_ioapic_irq (unsigned int irq)
1290 {
1291 unsigned long v;
1292 int i;
1293
1294 /*
1295 * It appears there is an erratum which affects at least version 0x11
1296 * of I/O APIC (that's the 82093AA and cores integrated into various
1297 * chipsets). Under certain conditions a level-triggered interrupt is
1298 * erroneously delivered as edge-triggered one but the respective IRR
1299 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1300 * message but it will never arrive and further interrupts are blocked
1301 * from the source. The exact reason is so far unknown, but the
1302 * phenomenon was observed when two consecutive interrupt requests
1303 * from a given source get delivered to the same CPU and the source is
1304 * temporarily disabled in between.
1305 *
1306 * A workaround is to simulate an EOI message manually. We achieve it
1307 * by setting the trigger mode to edge and then to level when the edge
1308 * trigger mode gets detected in the TMR of a local APIC for a
1309 * level-triggered interrupt. We mask the source for the time of the
1310 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1311 * The idea is from Manfred Spraul. --macro
1312 */
1313 i = IO_APIC_VECTOR(irq);
1314 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1315
1316 ack_APIC_irq();
1317
1318 if (!(v & (1 << (i & 0x1f)))) {
1319 #ifdef APIC_LOCKUP_DEBUG
1320 struct irq_pin_list *entry;
1321 #endif
1322
1323 #ifdef APIC_MISMATCH_DEBUG
1324 atomic_inc(&irq_mis_count);
1325 #endif
1326 spin_lock(&ioapic_lock);
1327 __mask_and_edge_IO_APIC_irq(irq);
1328 #ifdef APIC_LOCKUP_DEBUG
1329 for (entry = irq_2_pin + irq;;) {
1330 unsigned int reg;
1331
1332 if (entry->pin == -1)
1333 break;
1334 reg = io_apic_read(entry->apic, 0x10 + entry->pin * 2);
1335 if (reg & 0x00004000)
1336 printk(KERN_CRIT "Aieee!!! Remote IRR"
1337 " still set after unlock!\n");
1338 if (!entry->next)
1339 break;
1340 entry = irq_2_pin + entry->next;
1341 }
1342 #endif
1343 __unmask_and_level_IO_APIC_irq(irq);
1344 spin_unlock(&ioapic_lock);
1345 }
1346 }
1347
mask_and_ack_level_ioapic_irq(unsigned int irq)1348 static void mask_and_ack_level_ioapic_irq (unsigned int irq) { /* nothing */ }
1349
1350 #ifndef CONFIG_SMP
1351
send_IPI_self(int vector)1352 void fastcall send_IPI_self(int vector)
1353 {
1354 unsigned int cfg;
1355
1356 /*
1357 * Wait for idle.
1358 */
1359 apic_wait_icr_idle();
1360 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
1361 /*
1362 * Send the IPI. The write to APIC_ICR fires this off.
1363 */
1364 apic_write_around(APIC_ICR, cfg);
1365 }
1366
1367 #endif /* CONFIG_SMP */
1368
set_ioapic_affinity(unsigned int irq,unsigned long mask)1369 static void set_ioapic_affinity (unsigned int irq, unsigned long mask)
1370 {
1371 unsigned long flags;
1372
1373 /* pick a single cpu for clustered xapics */
1374 if(clustered_apic_mode == CLUSTERED_APIC_XAPIC){
1375 int cpu = ffs(mask)-1;
1376 mask = cpu_to_physical_apicid(cpu);
1377 }
1378
1379 /*
1380 * Only the first 8 bits are valid.
1381 */
1382 mask = mask << 24;
1383
1384 spin_lock_irqsave(&ioapic_lock, flags);
1385 __DO_ACTION(1, = mask, )
1386 spin_unlock_irqrestore(&ioapic_lock, flags);
1387 }
1388
1389 /*
1390 * Level and edge triggered IO-APIC interrupts need different handling,
1391 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1392 * handled with the level-triggered descriptor, but that one has slightly
1393 * more overhead. Level-triggered interrupts cannot be handled with the
1394 * edge-triggered handler, without risking IRQ storms and other ugly
1395 * races.
1396 */
1397
1398 static struct hw_interrupt_type ioapic_edge_irq_type = {
1399 "IO-APIC-edge",
1400 startup_edge_ioapic_irq,
1401 shutdown_edge_ioapic_irq,
1402 enable_edge_ioapic_irq,
1403 disable_edge_ioapic_irq,
1404 ack_edge_ioapic_irq,
1405 end_edge_ioapic_irq,
1406 set_ioapic_affinity,
1407 };
1408
1409 static struct hw_interrupt_type ioapic_level_irq_type = {
1410 "IO-APIC-level",
1411 startup_level_ioapic_irq,
1412 shutdown_level_ioapic_irq,
1413 enable_level_ioapic_irq,
1414 disable_level_ioapic_irq,
1415 mask_and_ack_level_ioapic_irq,
1416 end_level_ioapic_irq,
1417 set_ioapic_affinity,
1418 };
1419
init_IO_APIC_traps(void)1420 static inline void init_IO_APIC_traps(void)
1421 {
1422 int irq;
1423
1424 /*
1425 * NOTE! The local APIC isn't very good at handling
1426 * multiple interrupts at the same interrupt level.
1427 * As the interrupt level is determined by taking the
1428 * vector number and shifting that right by 4, we
1429 * want to spread these out a bit so that they don't
1430 * all fall in the same interrupt level.
1431 *
1432 * Also, we've got to be careful not to trash gate
1433 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1434 */
1435 for (irq = 0; irq < NR_IRQS ; irq++) {
1436 if (IO_APIC_IRQ(irq) && !IO_APIC_VECTOR(irq)) {
1437 /*
1438 * Hmm.. We don't have an entry for this,
1439 * so default to an old-fashioned 8259
1440 * interrupt if we can..
1441 */
1442 if (irq < 16)
1443 make_8259A_irq(irq);
1444 else
1445 /* Strange. Oh, well.. */
1446 irq_desc[irq].handler = &no_irq_type;
1447 }
1448 }
1449 }
1450
enable_lapic_irq(unsigned int irq)1451 static void enable_lapic_irq (unsigned int irq)
1452 {
1453 unsigned long v;
1454
1455 v = apic_read(APIC_LVT0);
1456 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1457 }
1458
disable_lapic_irq(unsigned int irq)1459 static void disable_lapic_irq (unsigned int irq)
1460 {
1461 unsigned long v;
1462
1463 v = apic_read(APIC_LVT0);
1464 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1465 }
1466
ack_lapic_irq(unsigned int irq)1467 static void ack_lapic_irq (unsigned int irq)
1468 {
1469 ack_APIC_irq();
1470 }
1471
end_lapic_irq(unsigned int i)1472 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1473
1474 static struct hw_interrupt_type lapic_irq_type = {
1475 "local-APIC-edge",
1476 NULL, /* startup_irq() not used for IRQ0 */
1477 NULL, /* shutdown_irq() not used for IRQ0 */
1478 enable_lapic_irq,
1479 disable_lapic_irq,
1480 ack_lapic_irq,
1481 end_lapic_irq
1482 };
1483
enable_NMI_through_LVT0(void * dummy)1484 static void enable_NMI_through_LVT0 (void * dummy)
1485 {
1486 unsigned int v, ver;
1487
1488 ver = apic_read(APIC_LVR);
1489 ver = GET_APIC_VERSION(ver);
1490 v = APIC_DM_NMI; /* unmask and set to NMI */
1491 if (!APIC_INTEGRATED(ver)) /* 82489DX */
1492 v |= APIC_LVT_LEVEL_TRIGGER;
1493 apic_write_around(APIC_LVT0, v);
1494 }
1495
setup_nmi(void)1496 static void setup_nmi (void)
1497 {
1498 /*
1499 * Dirty trick to enable the NMI watchdog ...
1500 * We put the 8259A master into AEOI mode and
1501 * unmask on all local APICs LVT0 as NMI.
1502 *
1503 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1504 * is from Maciej W. Rozycki - so we do not have to EOI from
1505 * the NMI handler or the timer interrupt.
1506 */
1507 printk(KERN_INFO "activating NMI Watchdog ...");
1508
1509 smp_call_function(enable_NMI_through_LVT0, NULL, 1, 1);
1510 enable_NMI_through_LVT0(NULL);
1511
1512 printk(" done.\n");
1513 }
1514
1515 /*
1516 * This looks a bit hackish but it's about the only one way of sending
1517 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1518 * not support the ExtINT mode, unfortunately. We need to send these
1519 * cycles as some i82489DX-based boards have glue logic that keeps the
1520 * 8259A interrupt line asserted until INTA. --macro
1521 */
unlock_ExtINT_logic(void)1522 static inline void unlock_ExtINT_logic(void)
1523 {
1524 int pin, i;
1525 struct IO_APIC_route_entry entry0, entry1;
1526 unsigned char save_control, save_freq_select;
1527 unsigned long flags;
1528
1529 pin = find_isa_irq_pin(8, mp_INT);
1530 if (pin == -1)
1531 return;
1532
1533 spin_lock_irqsave(&ioapic_lock, flags);
1534 *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1535 *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1536 spin_unlock_irqrestore(&ioapic_lock, flags);
1537 clear_IO_APIC_pin(0, pin);
1538
1539 memset(&entry1, 0, sizeof(entry1));
1540
1541 entry1.dest_mode = 0; /* physical delivery */
1542 entry1.mask = 0; /* unmask IRQ now */
1543 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1544 entry1.delivery_mode = dest_ExtINT;
1545 entry1.polarity = entry0.polarity;
1546 entry1.trigger = 0;
1547 entry1.vector = 0;
1548
1549 spin_lock_irqsave(&ioapic_lock, flags);
1550 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1551 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1552 spin_unlock_irqrestore(&ioapic_lock, flags);
1553
1554 save_control = CMOS_READ(RTC_CONTROL);
1555 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1556 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1557 RTC_FREQ_SELECT);
1558 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1559
1560 i = 100;
1561 while (i-- > 0) {
1562 mdelay(10);
1563 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1564 i -= 10;
1565 }
1566
1567 CMOS_WRITE(save_control, RTC_CONTROL);
1568 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1569 clear_IO_APIC_pin(0, pin);
1570
1571 spin_lock_irqsave(&ioapic_lock, flags);
1572 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1573 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1574 spin_unlock_irqrestore(&ioapic_lock, flags);
1575 }
1576
1577 /*
1578 * This code may look a bit paranoid, but it's supposed to cooperate with
1579 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1580 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1581 * fanatically on his truly buggy board.
1582 */
check_timer(void)1583 static inline void check_timer(void)
1584 {
1585 extern int timer_ack;
1586 int pin1, pin2;
1587 int vector;
1588
1589 /*
1590 * get/set the timer IRQ vector:
1591 */
1592 disable_8259A_irq(0);
1593 vector = assign_irq_vector(0);
1594 set_intr_gate(vector, interrupt[0]);
1595
1596 /*
1597 * Subtle, code in do_timer_interrupt() expects an AEOI
1598 * mode for the 8259A whenever interrupts are routed
1599 * through I/O APICs. Also IRQ0 has to be enabled in
1600 * the 8259A which implies the virtual wire has to be
1601 * disabled in the local APIC.
1602 */
1603 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1604 init_8259A(1);
1605 timer_ack = 1;
1606 enable_8259A_irq(0);
1607
1608 pin1 = find_isa_irq_pin(0, mp_INT);
1609 pin2 = find_isa_irq_pin(0, mp_ExtINT);
1610
1611 printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1612
1613 if (pin1 != -1) {
1614 /*
1615 * Ok, does IRQ0 through the IOAPIC work?
1616 */
1617 unmask_IO_APIC_irq(0);
1618 if (timer_irq_works()) {
1619 if (nmi_watchdog == NMI_IO_APIC) {
1620 disable_8259A_irq(0);
1621 setup_nmi();
1622 enable_8259A_irq(0);
1623 check_nmi_watchdog();
1624 }
1625 return;
1626 }
1627 clear_IO_APIC_pin(0, pin1);
1628 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1629 }
1630
1631 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1632 if (pin2 != -1) {
1633 printk("\n..... (found pin %d) ...", pin2);
1634 /*
1635 * legacy devices should be connected to IO APIC #0
1636 */
1637 setup_ExtINT_IRQ0_pin(pin2, vector);
1638 if (timer_irq_works()) {
1639 printk("works.\n");
1640 if (pin1 != -1)
1641 replace_pin_at_irq(0, 0, pin1, 0, pin2);
1642 else
1643 add_pin_to_irq(0, 0, pin2);
1644 if (nmi_watchdog == NMI_IO_APIC) {
1645 setup_nmi();
1646 check_nmi_watchdog();
1647 }
1648 return;
1649 }
1650 /*
1651 * Cleanup, just in case ...
1652 */
1653 clear_IO_APIC_pin(0, pin2);
1654 }
1655 printk(" failed.\n");
1656
1657 if (nmi_watchdog) {
1658 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1659 nmi_watchdog = 0;
1660 }
1661
1662 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1663
1664 disable_8259A_irq(0);
1665 irq_desc[0].handler = &lapic_irq_type;
1666 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1667 enable_8259A_irq(0);
1668
1669 if (timer_irq_works()) {
1670 printk(" works.\n");
1671 return;
1672 }
1673 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1674 printk(" failed.\n");
1675
1676 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1677
1678 init_8259A(0);
1679 make_8259A_irq(0);
1680 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1681
1682 unlock_ExtINT_logic();
1683
1684 if (timer_irq_works()) {
1685 printk(" works.\n");
1686 return;
1687 }
1688 printk(" failed :(.\n");
1689 panic("IO-APIC + timer doesn't work! pester mingo@redhat.com");
1690 }
1691
1692 /*
1693 *
1694 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1695 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1696 * Linux doesn't really care, as it's not actually used
1697 * for any interrupt handling anyway.
1698 */
1699 #define PIC_IRQS (1<<2)
1700
setup_IO_APIC(void)1701 void __init setup_IO_APIC(void)
1702 {
1703 enable_IO_APIC();
1704
1705 if (acpi_ioapic)
1706 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1707 else
1708 io_apic_irqs = ~PIC_IRQS;
1709
1710 printk("ENABLING IO-APIC IRQs\n");
1711
1712 /*
1713 * Set up IO-APIC IRQ routing.
1714 */
1715 if (!acpi_ioapic)
1716 setup_ioapic_ids_from_mpc();
1717 sync_Arb_IDs();
1718 setup_IO_APIC_irqs();
1719 init_IO_APIC_traps();
1720 check_timer();
1721 if (!acpi_ioapic)
1722 print_IO_APIC();
1723 }
1724
1725
1726 /* --------------------------------------------------------------------------
1727 ACPI-based IOAPIC Configuration
1728 -------------------------------------------------------------------------- */
1729
1730 #ifdef CONFIG_ACPI_BOOT
1731
1732 #define IO_APIC_MAX_ID 15
1733
io_apic_get_unique_id(int ioapic,int apic_id)1734 int __init io_apic_get_unique_id (int ioapic, int apic_id)
1735 {
1736 struct IO_APIC_reg_00 reg_00;
1737 static unsigned long apic_id_map = 0;
1738 unsigned long flags;
1739 int i = 0;
1740
1741 /*
1742 * The P4 platform supports up to 256 APIC IDs on two separate APIC
1743 * buses (one for LAPICs, one for IOAPICs), where predecessors only
1744 * supports up to 16 on one shared APIC bus.
1745 *
1746 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
1747 * advantage of new APIC bus architecture.
1748 */
1749
1750 if (!apic_id_map)
1751 apic_id_map = phys_cpu_present_map;
1752
1753 spin_lock_irqsave(&ioapic_lock, flags);
1754 *(int *)®_00 = io_apic_read(ioapic, 0);
1755 spin_unlock_irqrestore(&ioapic_lock, flags);
1756
1757 if (apic_id >= IO_APIC_MAX_ID) {
1758 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
1759 "%d\n", ioapic, apic_id, reg_00.ID);
1760 apic_id = reg_00.ID;
1761 }
1762
1763 /* XAPICs do not need unique IDs */
1764 if (clustered_apic_mode == CLUSTERED_APIC_XAPIC){
1765 printk(KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n",
1766 ioapic, apic_id);
1767 return apic_id;
1768 }
1769
1770 /*
1771 * Every APIC in a system must have a unique ID or we get lots of nice
1772 * 'stuck on smp_invalidate_needed IPI wait' messages.
1773 */
1774 if (apic_id_map & (1 << apic_id)) {
1775
1776 for (i = 0; i < IO_APIC_MAX_ID; i++) {
1777 if (!(apic_id_map & (1 << i)))
1778 break;
1779 }
1780
1781 if (i == IO_APIC_MAX_ID)
1782 panic("Max apic_id exceeded!\n");
1783
1784 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
1785 "trying %d\n", ioapic, apic_id, i);
1786
1787 apic_id = i;
1788 }
1789
1790 apic_id_map |= (1 << apic_id);
1791
1792 if (reg_00.ID != apic_id) {
1793 reg_00.ID = apic_id;
1794
1795 spin_lock_irqsave(&ioapic_lock, flags);
1796 io_apic_write(ioapic, 0, *(int *)®_00);
1797 *(int *)®_00 = io_apic_read(ioapic, 0);
1798 spin_unlock_irqrestore(&ioapic_lock, flags);
1799
1800 /* Sanity check */
1801 if (reg_00.ID != apic_id)
1802 panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
1803 }
1804
1805 printk(KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
1806
1807 return apic_id;
1808 }
1809
1810
io_apic_get_version(int ioapic)1811 int __init io_apic_get_version (int ioapic)
1812 {
1813 struct IO_APIC_reg_01 reg_01;
1814 unsigned long flags;
1815
1816 spin_lock_irqsave(&ioapic_lock, flags);
1817 *(int *)®_01 = io_apic_read(ioapic, 1);
1818 spin_unlock_irqrestore(&ioapic_lock, flags);
1819
1820 return reg_01.version;
1821 }
1822
1823
io_apic_get_redir_entries(int ioapic)1824 int __init io_apic_get_redir_entries (int ioapic)
1825 {
1826 struct IO_APIC_reg_01 reg_01;
1827 unsigned long flags;
1828
1829 spin_lock_irqsave(&ioapic_lock, flags);
1830 *(int *)®_01 = io_apic_read(ioapic, 1);
1831 spin_unlock_irqrestore(&ioapic_lock, flags);
1832
1833 return reg_01.entries;
1834 }
1835
1836
io_apic_set_pci_routing(int ioapic,int pin,int irq,int edge_level,int active_high_low)1837 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1838 {
1839 struct IO_APIC_route_entry entry;
1840 unsigned long flags;
1841
1842 if (!IO_APIC_IRQ(irq)) {
1843 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0/n",
1844 ioapic);
1845 return -EINVAL;
1846 }
1847
1848 /*
1849 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1850 * Note that we mask (disable) IRQs now -- these get enabled when the
1851 * corresponding device driver registers for this IRQ.
1852 */
1853
1854 memset(&entry,0,sizeof(entry));
1855
1856 entry.delivery_mode = dest_LowestPrio;
1857 entry.dest_mode = INT_DELIVERY_MODE;
1858 entry.dest.logical.logical_dest = target_cpus();
1859 entry.mask = 1; /* Disabled (masked) */
1860 entry.trigger = edge_level;
1861 entry.polarity = active_high_low;
1862
1863 /*
1864 * IRQs < 16 are already in the irq_2_pin[] map
1865 */
1866 if (irq >= 16)
1867 add_pin_to_irq(irq, ioapic, pin);
1868
1869 entry.vector = assign_irq_vector(irq);
1870
1871 Dprintk(KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1872 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1873 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq, edge_level, active_high_low);
1874
1875 if (edge_level) {
1876 irq_desc[irq].handler = &ioapic_level_irq_type;
1877 } else {
1878 irq_desc[irq].handler = &ioapic_edge_irq_type;
1879 }
1880
1881 set_intr_gate(entry.vector, interrupt[irq]);
1882
1883 if (!ioapic && (irq < 16))
1884 disable_8259A_irq(irq);
1885
1886 spin_lock_irqsave(&ioapic_lock, flags);
1887 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
1888 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
1889 spin_unlock_irqrestore(&ioapic_lock, flags);
1890
1891 return 0;
1892 }
1893
1894 #endif /*CONFIG_ACPI_BOOT*/
1895