1 #include <linux/config.h>
2 #include <linux/ptrace.h>
3 #include <linux/errno.h>
4 #include <linux/signal.h>
5 #include <linux/sched.h>
6 #include <linux/ioport.h>
7 #include <linux/interrupt.h>
8 #include <linux/timex.h>
9 #include <linux/slab.h>
10 #include <linux/random.h>
11 #include <linux/smp_lock.h>
12 #include <linux/init.h>
13 #include <linux/kernel_stat.h>
14
15 #include <asm/acpi.h>
16 #include <asm/atomic.h>
17 #include <asm/system.h>
18 #include <asm/io.h>
19 #include <asm/irq.h>
20 #include <asm/bitops.h>
21 #include <asm/pgtable.h>
22 #include <asm/delay.h>
23 #include <asm/desc.h>
24 #include <asm/apic.h>
25
26 #include <linux/irq.h>
27
28 /*
29 * Common place to define all x86 IRQ vectors
30 *
31 * This builds up the IRQ handler stubs using some ugly macros in irq.h
32 *
33 * These macros create the low-level assembly IRQ routines that save
34 * register context and call do_IRQ(). do_IRQ() then does all the
35 * operations that are needed to keep the AT (or SMP IOAPIC)
36 * interrupt-controller happy.
37 */
38
39 BUILD_COMMON_IRQ()
40
41 #define BI(x,y) \
42 BUILD_IRQ(x##y)
43
44 #define BUILD_16_IRQS(x) \
45 BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
46 BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
47 BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
48 BI(x,c) BI(x,d) BI(x,e) BI(x,f)
49
50 /*
51 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
52 * (these are usually mapped to vectors 0x20-0x2f)
53 */
54 BUILD_16_IRQS(0x0)
55
56 #ifdef CONFIG_X86_IO_APIC
57 /*
58 * The IO-APIC gives us many more interrupt sources. Most of these
59 * are unused but an SMP system is supposed to have enough memory ...
60 * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
61 * across the spectrum, so we really want to be prepared to get all
62 * of these. Plus, more powerful systems might have more than 64
63 * IO-APIC registers.
64 *
65 * (these are usually mapped into the 0x30-0xff vector range)
66 */
67 BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
68 BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
69 BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
70 BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd)
71 #endif
72
73 #undef BUILD_16_IRQS
74 #undef BI
75
76
77 /*
78 * The following vectors are part of the Linux architecture, there
79 * is no hardware IRQ pin equivalent for them, they are triggered
80 * through the ICC by us (IPIs)
81 */
82 #ifdef CONFIG_SMP
83 BUILD_SMP_INTERRUPT(reschedule_interrupt,RESCHEDULE_VECTOR)
84 BUILD_SMP_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR)
85 BUILD_SMP_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR)
86 #endif
87
88 /*
89 * every pentium local APIC has two 'local interrupts', with a
90 * soft-definable vector attached to both interrupts, one of
91 * which is a timer interrupt, the other one is error counter
92 * overflow. Linux uses the local APIC timer interrupt to get
93 * a much simpler SMP time architecture:
94 */
95 #ifdef CONFIG_X86_LOCAL_APIC
96 BUILD_SMP_TIMER_INTERRUPT(apic_timer_interrupt,LOCAL_TIMER_VECTOR)
97 BUILD_SMP_INTERRUPT(error_interrupt,ERROR_APIC_VECTOR)
98 BUILD_SMP_INTERRUPT(spurious_interrupt,SPURIOUS_APIC_VECTOR)
99 #endif
100
101 #define IRQ(x,y) \
102 IRQ##x##y##_interrupt
103
104 #define IRQLIST_16(x) \
105 IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
106 IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
107 IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
108 IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
109
110 void (*interrupt[NR_IRQS])(void) = {
111 IRQLIST_16(0x0),
112
113 #ifdef CONFIG_X86_IO_APIC
114 IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
115 IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
116 IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
117 IRQLIST_16(0xc), IRQLIST_16(0xd)
118 #endif
119 };
120
121 #undef IRQ
122 #undef IRQLIST_16
123
124 /*
125 * This is the 'legacy' 8259A Programmable Interrupt Controller,
126 * present in the majority of PC/AT boxes.
127 * plus some generic x86 specific things if generic specifics makes
128 * any sense at all.
129 * this file should become arch/i386/kernel/irq.c when the old irq.c
130 * moves to arch independent land
131 */
132
133 spinlock_t i8259A_lock = SPIN_LOCK_UNLOCKED;
134
end_8259A_irq(unsigned int irq)135 static void end_8259A_irq (unsigned int irq)
136 {
137 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
138 enable_8259A_irq(irq);
139 }
140
141 #define shutdown_8259A_irq disable_8259A_irq
142
143 void mask_and_ack_8259A(unsigned int);
144
startup_8259A_irq(unsigned int irq)145 static unsigned int startup_8259A_irq(unsigned int irq)
146 {
147 enable_8259A_irq(irq);
148 return 0; /* never anything pending */
149 }
150
151 static struct hw_interrupt_type i8259A_irq_type = {
152 "XT-PIC",
153 startup_8259A_irq,
154 shutdown_8259A_irq,
155 enable_8259A_irq,
156 disable_8259A_irq,
157 mask_and_ack_8259A,
158 end_8259A_irq,
159 NULL
160 };
161
162 /*
163 * 8259A PIC functions to handle ISA devices:
164 */
165
166 /*
167 * This contains the irq mask for both 8259A irq controllers,
168 */
169 static unsigned int cached_irq_mask = 0xffff;
170
171 #define __byte(x,y) (((unsigned char *)&(y))[x])
172 #define cached_21 (__byte(0,cached_irq_mask))
173 #define cached_A1 (__byte(1,cached_irq_mask))
174
175 /*
176 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
177 * boards the timer interrupt is not really connected to any IO-APIC pin,
178 * it's fed to the master 8259A's IR0 line only.
179 *
180 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
181 * this 'mixed mode' IRQ handling costs nothing because it's only used
182 * at IRQ setup time.
183 */
184 unsigned long io_apic_irqs;
185
disable_8259A_irq(unsigned int irq)186 void disable_8259A_irq(unsigned int irq)
187 {
188 unsigned int mask = 1 << irq;
189 unsigned long flags;
190
191 spin_lock_irqsave(&i8259A_lock, flags);
192 cached_irq_mask |= mask;
193 if (irq & 8)
194 outb(cached_A1,0xA1);
195 else
196 outb(cached_21,0x21);
197 spin_unlock_irqrestore(&i8259A_lock, flags);
198 }
199
enable_8259A_irq(unsigned int irq)200 void enable_8259A_irq(unsigned int irq)
201 {
202 unsigned int mask = ~(1 << irq);
203 unsigned long flags;
204
205 spin_lock_irqsave(&i8259A_lock, flags);
206 cached_irq_mask &= mask;
207 if (irq & 8)
208 outb(cached_A1,0xA1);
209 else
210 outb(cached_21,0x21);
211 spin_unlock_irqrestore(&i8259A_lock, flags);
212 }
213
i8259A_irq_pending(unsigned int irq)214 int i8259A_irq_pending(unsigned int irq)
215 {
216 unsigned int mask = 1<<irq;
217 unsigned long flags;
218 int ret;
219
220 spin_lock_irqsave(&i8259A_lock, flags);
221 if (irq < 8)
222 ret = inb(0x20) & mask;
223 else
224 ret = inb(0xA0) & (mask >> 8);
225 spin_unlock_irqrestore(&i8259A_lock, flags);
226
227 return ret;
228 }
229
make_8259A_irq(unsigned int irq)230 void make_8259A_irq(unsigned int irq)
231 {
232 disable_irq_nosync(irq);
233 io_apic_irqs &= ~(1<<irq);
234 irq_desc[irq].handler = &i8259A_irq_type;
235 enable_irq(irq);
236 }
237
238 /*
239 * This function assumes to be called rarely. Switching between
240 * 8259A registers is slow.
241 * This has to be protected by the irq controller spinlock
242 * before being called.
243 */
i8259A_irq_real(unsigned int irq)244 static inline int i8259A_irq_real(unsigned int irq)
245 {
246 int value;
247 int irqmask = 1<<irq;
248
249 if (irq < 8) {
250 outb(0x0B,0x20); /* ISR register */
251 value = inb(0x20) & irqmask;
252 outb(0x0A,0x20); /* back to the IRR register */
253 return value;
254 }
255 outb(0x0B,0xA0); /* ISR register */
256 value = inb(0xA0) & (irqmask >> 8);
257 outb(0x0A,0xA0); /* back to the IRR register */
258 return value;
259 }
260
261 /*
262 * Careful! The 8259A is a fragile beast, it pretty
263 * much _has_ to be done exactly like this (mask it
264 * first, _then_ send the EOI, and the order of EOI
265 * to the two 8259s is important!
266 */
mask_and_ack_8259A(unsigned int irq)267 void mask_and_ack_8259A(unsigned int irq)
268 {
269 unsigned int irqmask = 1 << irq;
270 unsigned long flags;
271
272 spin_lock_irqsave(&i8259A_lock, flags);
273 /*
274 * Lightweight spurious IRQ detection. We do not want
275 * to overdo spurious IRQ handling - it's usually a sign
276 * of hardware problems, so we only do the checks we can
277 * do without slowing down good hardware unnecesserily.
278 *
279 * Note that IRQ7 and IRQ15 (the two spurious IRQs
280 * usually resulting from the 8259A-1|2 PICs) occur
281 * even if the IRQ is masked in the 8259A. Thus we
282 * can check spurious 8259A IRQs without doing the
283 * quite slow i8259A_irq_real() call for every IRQ.
284 * This does not cover 100% of spurious interrupts,
285 * but should be enough to warn the user that there
286 * is something bad going on ...
287 */
288 if (cached_irq_mask & irqmask)
289 goto spurious_8259A_irq;
290 cached_irq_mask |= irqmask;
291
292 handle_real_irq:
293 if (irq & 8) {
294 inb(0xA1); /* DUMMY - (do we need this?) */
295 outb(cached_A1,0xA1);
296 outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */
297 outb(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */
298 } else {
299 inb(0x21); /* DUMMY - (do we need this?) */
300 outb(cached_21,0x21);
301 outb(0x60+irq,0x20); /* 'Specific EOI' to master */
302 }
303 spin_unlock_irqrestore(&i8259A_lock, flags);
304 return;
305
306 spurious_8259A_irq:
307 /*
308 * this is the slow path - should happen rarely.
309 */
310 if (i8259A_irq_real(irq))
311 /*
312 * oops, the IRQ _is_ in service according to the
313 * 8259A - not spurious, go handle it.
314 */
315 goto handle_real_irq;
316
317 {
318 static int spurious_irq_mask;
319 /*
320 * At this point we can be sure the IRQ is spurious,
321 * lets ACK and report it. [once per IRQ]
322 */
323 if (!(spurious_irq_mask & irqmask)) {
324 printk("spurious 8259A interrupt: IRQ%d.\n", irq);
325 spurious_irq_mask |= irqmask;
326 }
327 atomic_inc(&irq_err_count);
328 /*
329 * Theoretically we do not have to handle this IRQ,
330 * but in Linux this does not cause problems and is
331 * simpler for us.
332 */
333 goto handle_real_irq;
334 }
335 }
336
init_8259A(int auto_eoi)337 void __init init_8259A(int auto_eoi)
338 {
339 unsigned long flags;
340
341 spin_lock_irqsave(&i8259A_lock, flags);
342
343 outb(0xff, 0x21); /* mask all of 8259A-1 */
344 outb(0xff, 0xA1); /* mask all of 8259A-2 */
345
346 /*
347 * outb_p - this has to work on a wide range of PC hardware.
348 */
349 outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */
350 outb_p(0x20 + 0, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
351 outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */
352 if (auto_eoi)
353 outb_p(0x03, 0x21); /* master does Auto EOI */
354 else
355 outb_p(0x01, 0x21); /* master expects normal EOI */
356
357 outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */
358 outb_p(0x20 + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
359 outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */
360 outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode
361 is to be investigated) */
362
363 if (auto_eoi)
364 /*
365 * in AEOI mode we just have to mask the interrupt
366 * when acking.
367 */
368 i8259A_irq_type.ack = disable_8259A_irq;
369 else
370 i8259A_irq_type.ack = mask_and_ack_8259A;
371
372 udelay(100); /* wait for 8259A to initialize */
373
374 outb(cached_21, 0x21); /* restore master IRQ mask */
375 outb(cached_A1, 0xA1); /* restore slave IRQ mask */
376
377 spin_unlock_irqrestore(&i8259A_lock, flags);
378 }
379
380 /*
381 * Note that on a 486, we don't want to do a SIGFPE on an irq13
382 * as the irq is unreliable, and exception 16 works correctly
383 * (ie as explained in the intel literature). On a 386, you
384 * can't use exception 16 due to bad IBM design, so we have to
385 * rely on the less exact irq13.
386 *
387 * Careful.. Not only is IRQ13 unreliable, but it is also
388 * leads to races. IBM designers who came up with it should
389 * be shot.
390 */
391
math_error_irq(int cpl,void * dev_id,struct pt_regs * regs)392 static void math_error_irq(int cpl, void *dev_id, struct pt_regs *regs)
393 {
394 extern void math_error(void *);
395 outb(0,0xF0);
396 if (ignore_irq13 || !boot_cpu_data.hard_math)
397 return;
398 math_error((void *)regs->eip);
399 }
400
401 /*
402 * New motherboards sometimes make IRQ 13 be a PCI interrupt,
403 * so allow interrupt sharing.
404 */
405 static struct irqaction irq13 = { math_error_irq, 0, 0, "fpu", NULL, NULL };
406
407 /*
408 * IRQ2 is cascade interrupt to second interrupt controller
409 */
410
411 #ifndef CONFIG_VISWS
412 static struct irqaction irq2 = { no_action, 0, 0, "cascade", NULL, NULL};
413 #endif
414
415
init_ISA_irqs(void)416 void __init init_ISA_irqs (void)
417 {
418 int i;
419
420 #ifdef CONFIG_X86_LOCAL_APIC
421 init_bsp_APIC();
422 #endif
423 init_8259A(0);
424
425 for (i = 0; i < NR_IRQS; i++) {
426 irq_desc[i].status = IRQ_DISABLED;
427 irq_desc[i].action = 0;
428 irq_desc[i].depth = 1;
429
430 if (i < 16) {
431 /*
432 * 16 old-style INTA-cycle interrupts:
433 */
434 irq_desc[i].handler = &i8259A_irq_type;
435 } else {
436 /*
437 * 'high' PCI IRQs filled in on demand
438 */
439 irq_desc[i].handler = &no_irq_type;
440 }
441 }
442 }
443
init_IRQ(void)444 void __init init_IRQ(void)
445 {
446 int i;
447
448 #ifndef CONFIG_X86_VISWS_APIC
449 init_ISA_irqs();
450 #else
451 init_VISWS_APIC_irqs();
452 #endif
453 /*
454 * Cover the whole vector space, no vector can escape
455 * us. (some of these will be overridden and become
456 * 'special' SMP interrupts)
457 */
458 for (i = 0; i < NR_IRQS; i++) {
459 int vector = FIRST_EXTERNAL_VECTOR + i;
460 if (vector != SYSCALL_VECTOR)
461 set_intr_gate(vector, interrupt[i]);
462 }
463
464 #ifdef CONFIG_SMP
465 /*
466 * IRQ0 must be given a fixed assignment and initialized,
467 * because it's used before the IO-APIC is set up.
468 */
469 set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
470
471 /*
472 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
473 * IPI, driven by wakeup.
474 */
475 set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
476
477 /* IPI for invalidation */
478 set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
479
480 /* IPI for generic function call */
481 set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
482 #endif
483
484 #ifdef CONFIG_X86_LOCAL_APIC
485 /* self generated IPI for local APIC timer */
486 set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
487
488 /* IPI vectors for APIC spurious and error interrupts */
489 set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
490 set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
491 #endif
492
493 /*
494 * Set the clock to HZ Hz, we already have a valid
495 * vector now:
496 */
497 outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */
498 outb_p(LATCH & 0xff , 0x40); /* LSB */
499 outb(LATCH >> 8 , 0x40); /* MSB */
500
501 #ifndef CONFIG_VISWS
502 if (!acpi_ioapic)
503 setup_irq(2, &irq2);
504 #endif
505
506 /*
507 * External FPU? Set up irq13 if so, for
508 * original braindamaged IBM FERR coupling.
509 */
510 if (boot_cpu_data.hard_math && !cpu_has_fpu)
511 setup_irq(13, &irq13);
512 }
513