1 /*
2 * linux/arch/arm/kernel/dma-rpc.c
3 *
4 * Copyright (C) 1998 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * DMA functions specific to RiscPC architecture
11 */
12 #include <linux/sched.h>
13 #include <linux/slab.h>
14 #include <linux/mman.h>
15 #include <linux/init.h>
16 #include <linux/pci.h>
17
18 #include <asm/page.h>
19 #include <asm/dma.h>
20 #include <asm/fiq.h>
21 #include <asm/io.h>
22 #include <asm/irq.h>
23 #include <asm/hardware.h>
24 #include <asm/uaccess.h>
25
26 #include <asm/mach/dma.h>
27 #include <asm/hardware/iomd.h>
28
29 #if 0
30 typedef enum {
31 dma_size_8 = 1,
32 dma_size_16 = 2,
33 dma_size_32 = 4,
34 dma_size_128 = 16
35 } dma_size_t;
36
37 typedef struct {
38 dma_size_t transfersize;
39 } dma_t;
40 #endif
41
42 #define TRANSFER_SIZE 2
43
44 #define CURA (0)
45 #define ENDA (IOMD_IO0ENDA - IOMD_IO0CURA)
46 #define CURB (IOMD_IO0CURB - IOMD_IO0CURA)
47 #define ENDB (IOMD_IO0ENDB - IOMD_IO0CURA)
48 #define CR (IOMD_IO0CR - IOMD_IO0CURA)
49 #define ST (IOMD_IO0ST - IOMD_IO0CURA)
50
51 #define state_prog_a 0
52 #define state_wait_a 1
53 #define state_wait_b 2
54
iomd_get_next_sg(struct scatterlist * sg,dma_t * dma)55 static void iomd_get_next_sg(struct scatterlist *sg, dma_t *dma)
56 {
57 unsigned long end, offset, flags = 0;
58
59 if (dma->sg) {
60 sg->dma_address = dma->sg->dma_address;
61 offset = sg->dma_address & ~PAGE_MASK;
62
63 end = offset + dma->sg->length;
64
65 if (end > PAGE_SIZE)
66 end = PAGE_SIZE;
67
68 if (offset + (int) TRANSFER_SIZE > end)
69 flags |= DMA_END_L;
70
71 sg->length = end - TRANSFER_SIZE;
72
73 dma->sg->length -= end - offset;
74 dma->sg->dma_address += end - offset;
75
76 if (dma->sg->length == 0) {
77 if (dma->sgcount > 1) {
78 dma->sg++;
79 dma->sgcount--;
80 } else {
81 dma->sg = NULL;
82 flags |= DMA_END_S;
83 }
84 }
85 } else {
86 flags = DMA_END_S | DMA_END_L;
87 sg->dma_address = 0;
88 sg->length = 0;
89 }
90
91 sg->length |= flags;
92 }
93
iomd_dma_handle(int irq,void * dev_id,struct pt_regs * regs)94 static void iomd_dma_handle(int irq, void *dev_id, struct pt_regs *regs)
95 {
96 dma_t *dma = (dma_t *)dev_id;
97 unsigned long base = dma->dma_base;
98
99 do {
100 unsigned int status;
101
102 status = iomd_readb(base + ST);
103 if (!(status & DMA_ST_INT))
104 return;
105
106 if (status & DMA_ST_OFL && !dma->sg)
107 break;
108
109 iomd_get_next_sg(&dma->cur_sg, dma);
110
111 switch (status & (DMA_ST_OFL | DMA_ST_AB)) {
112 case DMA_ST_OFL: /* OIA */
113 case DMA_ST_AB: /* .IB */
114 iomd_writel(dma->cur_sg.dma_address, base + CURA);
115 iomd_writel(dma->cur_sg.length, base + ENDA);
116 break;
117
118 case DMA_ST_OFL | DMA_ST_AB: /* OIB */
119 case 0: /* .IA */
120 iomd_writel(dma->cur_sg.dma_address, base + CURB);
121 iomd_writel(dma->cur_sg.length, base + ENDB);
122 break;
123 }
124 } while (1);
125
126 iomd_writeb(0, base + CR);
127 disable_irq(irq);
128 }
129
iomd_request_dma(dmach_t channel,dma_t * dma)130 static int iomd_request_dma(dmach_t channel, dma_t *dma)
131 {
132 return request_irq(dma->dma_irq, iomd_dma_handle,
133 SA_INTERRUPT, dma->device_id, dma);
134 }
135
iomd_free_dma(dmach_t channel,dma_t * dma)136 static void iomd_free_dma(dmach_t channel, dma_t *dma)
137 {
138 free_irq(dma->dma_irq, dma);
139 }
140
iomd_enable_dma(dmach_t channel,dma_t * dma)141 static void iomd_enable_dma(dmach_t channel, dma_t *dma)
142 {
143 unsigned long dma_base = dma->dma_base;
144 unsigned int ctrl = TRANSFER_SIZE | DMA_CR_E;
145
146 if (dma->invalid) {
147 dma->invalid = 0;
148
149 /*
150 * Cope with ISA-style drivers which expect cache
151 * coherence.
152 */
153 if (!dma->using_sg) {
154 dma->buf.dma_address = pci_map_single(NULL,
155 dma->buf.address, dma->buf.length,
156 dma->dma_mode == DMA_MODE_READ ?
157 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE);
158 }
159
160 iomd_writeb(DMA_CR_C, dma_base + CR);
161 }
162
163 if (dma->dma_mode == DMA_MODE_READ)
164 ctrl |= DMA_CR_D;
165
166 iomd_writeb(ctrl, dma_base + CR);
167 enable_irq(dma->dma_irq);
168 }
169
iomd_disable_dma(dmach_t channel,dma_t * dma)170 static void iomd_disable_dma(dmach_t channel, dma_t *dma)
171 {
172 unsigned long dma_base = dma->dma_base;
173 unsigned long flags;
174 unsigned int ctrl;
175
176 local_irq_save(flags);
177 ctrl = iomd_readb(dma_base + CR);
178 if (ctrl & DMA_CR_E)
179 disable_irq(dma->dma_irq);
180 iomd_writeb(ctrl & ~DMA_CR_E, dma_base + CR);
181 local_irq_restore(flags);
182 }
183
iomd_set_dma_speed(dmach_t channel,dma_t * dma,int cycle)184 static int iomd_set_dma_speed(dmach_t channel, dma_t *dma, int cycle)
185 {
186 int tcr, speed;
187
188 if (cycle < 188)
189 speed = 3;
190 else if (cycle <= 250)
191 speed = 2;
192 else if (cycle < 438)
193 speed = 1;
194 else
195 speed = 0;
196
197 tcr = iomd_readb(IOMD_DMATCR);
198 speed &= 3;
199
200 switch (channel) {
201 case DMA_0:
202 tcr = (tcr & ~0x03) | speed;
203 break;
204
205 case DMA_1:
206 tcr = (tcr & ~0x0c) | (speed << 2);
207 break;
208
209 case DMA_2:
210 tcr = (tcr & ~0x30) | (speed << 4);
211 break;
212
213 case DMA_3:
214 tcr = (tcr & ~0xc0) | (speed << 6);
215 break;
216
217 default:
218 break;
219 }
220
221 iomd_writeb(tcr, IOMD_DMATCR);
222
223 return speed;
224 }
225
226 static struct dma_ops iomd_dma_ops = {
227 .type = "IOMD",
228 .request = iomd_request_dma,
229 .free = iomd_free_dma,
230 .enable = iomd_enable_dma,
231 .disable = iomd_disable_dma,
232 .setspeed = iomd_set_dma_speed,
233 };
234
235 static struct fiq_handler fh = {
236 .name = "floppydma"
237 };
238
floppy_enable_dma(dmach_t channel,dma_t * dma)239 static void floppy_enable_dma(dmach_t channel, dma_t *dma)
240 {
241 void *fiqhandler_start;
242 unsigned int fiqhandler_length;
243 struct pt_regs regs;
244
245 if (dma->dma_mode == DMA_MODE_READ) {
246 extern unsigned char floppy_fiqin_start, floppy_fiqin_end;
247 fiqhandler_start = &floppy_fiqin_start;
248 fiqhandler_length = &floppy_fiqin_end - &floppy_fiqin_start;
249 } else {
250 extern unsigned char floppy_fiqout_start, floppy_fiqout_end;
251 fiqhandler_start = &floppy_fiqout_start;
252 fiqhandler_length = &floppy_fiqout_end - &floppy_fiqout_start;
253 }
254
255 regs.ARM_r9 = dma->buf.length;
256 regs.ARM_r10 = (unsigned long)dma->buf.address;
257 regs.ARM_fp = FLOPPYDMA_BASE;
258
259 if (claim_fiq(&fh)) {
260 printk("floppydma: couldn't claim FIQ.\n");
261 return;
262 }
263
264 set_fiq_handler(fiqhandler_start, fiqhandler_length);
265 set_fiq_regs(®s);
266 enable_fiq(dma->dma_irq);
267 }
268
floppy_disable_dma(dmach_t channel,dma_t * dma)269 static void floppy_disable_dma(dmach_t channel, dma_t *dma)
270 {
271 disable_fiq(dma->dma_irq);
272 release_fiq(&fh);
273 }
274
floppy_get_residue(dmach_t channel,dma_t * dma)275 static int floppy_get_residue(dmach_t channel, dma_t *dma)
276 {
277 struct pt_regs regs;
278 get_fiq_regs(®s);
279 return regs.ARM_r9;
280 }
281
282 static struct dma_ops floppy_dma_ops = {
283 .type = "FIQDMA",
284 .enable = floppy_enable_dma,
285 .disable = floppy_disable_dma,
286 .residue = floppy_get_residue,
287 };
288
289 /*
290 * This is virtual DMA - we don't need anything here.
291 */
sound_enable_disable_dma(dmach_t channel,dma_t * dma)292 static void sound_enable_disable_dma(dmach_t channel, dma_t *dma)
293 {
294 }
295
296 static struct dma_ops sound_dma_ops = {
297 .type = "VIRTUAL",
298 .enable = sound_enable_disable_dma,
299 .disable = sound_enable_disable_dma,
300 };
301
arch_dma_init(dma_t * dma)302 void __init arch_dma_init(dma_t *dma)
303 {
304 iomd_writeb(0, IOMD_IO0CR);
305 iomd_writeb(0, IOMD_IO1CR);
306 iomd_writeb(0, IOMD_IO2CR);
307 iomd_writeb(0, IOMD_IO3CR);
308
309 iomd_writeb(0xa0, IOMD_DMATCR);
310
311 dma[DMA_0].dma_base = IOMD_IO0CURA;
312 dma[DMA_0].dma_irq = IRQ_DMA0;
313 dma[DMA_0].d_ops = &iomd_dma_ops;
314 dma[DMA_1].dma_base = IOMD_IO1CURA;
315 dma[DMA_1].dma_irq = IRQ_DMA1;
316 dma[DMA_1].d_ops = &iomd_dma_ops;
317 dma[DMA_2].dma_base = IOMD_IO2CURA;
318 dma[DMA_2].dma_irq = IRQ_DMA2;
319 dma[DMA_2].d_ops = &iomd_dma_ops;
320 dma[DMA_3].dma_base = IOMD_IO3CURA;
321 dma[DMA_3].dma_irq = IRQ_DMA3;
322 dma[DMA_3].d_ops = &iomd_dma_ops;
323 dma[DMA_S0].dma_base = IOMD_SD0CURA;
324 dma[DMA_S0].dma_irq = IRQ_DMAS0;
325 dma[DMA_S0].d_ops = &iomd_dma_ops;
326 dma[DMA_S1].dma_base = IOMD_SD1CURA;
327 dma[DMA_S1].dma_irq = IRQ_DMAS1;
328 dma[DMA_S1].d_ops = &iomd_dma_ops;
329 dma[DMA_VIRTUAL_FLOPPY].dma_irq = FIQ_FLOPPYDATA;
330 dma[DMA_VIRTUAL_FLOPPY].d_ops = &floppy_dma_ops;
331 dma[DMA_VIRTUAL_SOUND].d_ops = &sound_dma_ops;
332
333 /*
334 * Setup DMA channels 2,3 to be for podules
335 * and channels 0,1 for internal devices
336 */
337 iomd_writeb(DMA_EXT_IO3|DMA_EXT_IO2, IOMD_DMAEXT);
338 }
339