1 /*
2 * linux/arch/arm/kernel/bios32.c
3 *
4 * PCI bios-type initialisation for PCI machines
5 *
6 * Bits taken from various places.
7 */
8 #include <linux/config.h>
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/slab.h>
12 #include <linux/init.h>
13
14 #include <asm/page.h> /* for BUG() */
15 #include <asm/irq.h>
16 #include <asm/mach-types.h>
17 #include <asm/mach/pci.h>
18
19 static int debug_pci;
20 int have_isa_bridge;
21
22 struct pci_sys_data {
23 /*
24 * The hardware we are attached to
25 */
26 struct hw_pci *hw;
27
28 unsigned long mem_offset;
29
30 /*
31 * These are the resources for the root bus.
32 */
33 struct resource *resource[3];
34 };
35
pcibios_report_status(u_int status_mask,int warn)36 void pcibios_report_status(u_int status_mask, int warn)
37 {
38 struct pci_dev *dev;
39
40 pci_for_each_dev(dev) {
41 u16 status;
42
43 /*
44 * ignore host bridge - we handle
45 * that separately
46 */
47 if (dev->bus->number == 0 && dev->devfn == 0)
48 continue;
49
50 pci_read_config_word(dev, PCI_STATUS, &status);
51
52 status &= status_mask;
53 if (status == 0)
54 continue;
55
56 /* clear the status errors */
57 pci_write_config_word(dev, PCI_STATUS, status);
58
59 if (warn)
60 printk("(%02x:%02x.%d: %04X) ", dev->bus->number,
61 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
62 status);
63 }
64 }
65
66 /*
67 * We don't use this to fix the device, but initialisation of it.
68 * It's not the correct use for this, but it works.
69 * Note that the arbiter/ISA bridge appears to be buggy, specifically in
70 * the following area:
71 * 1. park on CPU
72 * 2. ISA bridge ping-pong
73 * 3. ISA bridge master handling of target RETRY
74 *
75 * Bug 3 is responsible for the sound DMA grinding to a halt. We now
76 * live with bug 2.
77 */
pci_fixup_83c553(struct pci_dev * dev)78 static void __init pci_fixup_83c553(struct pci_dev *dev)
79 {
80 /*
81 * Set memory region to start at address 0, and enable IO
82 */
83 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
84 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
85
86 dev->resource[0].end -= dev->resource[0].start;
87 dev->resource[0].start = 0;
88
89 /*
90 * All memory requests from ISA to be channelled to PCI
91 */
92 pci_write_config_byte(dev, 0x48, 0xff);
93
94 /*
95 * Enable ping-pong on bus master to ISA bridge transactions.
96 * This improves the sound DMA substantially. The fixed
97 * priority arbiter also helps (see below).
98 */
99 pci_write_config_byte(dev, 0x42, 0x01);
100
101 /*
102 * Enable PCI retry
103 */
104 pci_write_config_byte(dev, 0x40, 0x22);
105
106 /*
107 * We used to set the arbiter to "park on last master" (bit
108 * 1 set), but unfortunately the CyberPro does not park the
109 * bus. We must therefore park on CPU. Unfortunately, this
110 * may trigger yet another bug in the 553.
111 */
112 pci_write_config_byte(dev, 0x83, 0x02);
113
114 /*
115 * Make the ISA DMA request lowest priority, and disable
116 * rotating priorities completely.
117 */
118 pci_write_config_byte(dev, 0x80, 0x11);
119 pci_write_config_byte(dev, 0x81, 0x00);
120
121 /*
122 * Route INTA input to IRQ 11, and set IRQ11 to be level
123 * sensitive.
124 */
125 pci_write_config_word(dev, 0x44, 0xb000);
126 outb(0x08, 0x4d1);
127 }
128
pci_fixup_unassign(struct pci_dev * dev)129 static void __init pci_fixup_unassign(struct pci_dev *dev)
130 {
131 dev->resource[0].end -= dev->resource[0].start;
132 dev->resource[0].start = 0;
133 }
134
135 /*
136 * Prevent the PCI layer from seeing the resources allocated to this device
137 * if it is the host bridge by marking it as such. These resources are of
138 * no consequence to the PCI layer (they are handled elsewhere).
139 */
pci_fixup_dec21285(struct pci_dev * dev)140 static void __init pci_fixup_dec21285(struct pci_dev *dev)
141 {
142 int i;
143
144 if (dev->devfn == 0) {
145 dev->class &= 0xff;
146 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
147 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
148 dev->resource[i].start = 0;
149 dev->resource[i].end = 0;
150 dev->resource[i].flags = 0;
151 }
152 }
153 }
154
155 /*
156 * PCI IDE controllers use non-standard I/O port decoding, respect it.
157 */
pci_fixup_ide_bases(struct pci_dev * dev)158 static void __init pci_fixup_ide_bases(struct pci_dev *dev)
159 {
160 struct resource *r;
161 int i;
162
163 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
164 return;
165
166 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
167 r = dev->resource + i;
168 if ((r->start & ~0x80) == 0x374) {
169 r->start |= 2;
170 r->end = r->start;
171 }
172 }
173 }
174
175 /*
176 * Put the DEC21142 to sleep
177 */
pci_fixup_dec21142(struct pci_dev * dev)178 static void __init pci_fixup_dec21142(struct pci_dev *dev)
179 {
180 pci_write_config_dword(dev, 0x40, 0x80000000);
181 }
182
183 /*
184 * The CY82C693 needs some rather major fixups to ensure that it does
185 * the right thing. Idea from the Alpha people, with a few additions.
186 *
187 * We ensure that the IDE base registers are set to 1f0/3f4 for the
188 * primary bus, and 170/374 for the secondary bus. Also, hide them
189 * from the PCI subsystem view as well so we won't try to perform
190 * our own auto-configuration on them.
191 *
192 * In addition, we ensure that the PCI IDE interrupts are routed to
193 * IRQ 14 and IRQ 15 respectively.
194 *
195 * The above gets us to a point where the IDE on this device is
196 * functional. However, The CY82C693U _does not work_ in bus
197 * master mode without locking the PCI bus solid.
198 */
pci_fixup_cy82c693(struct pci_dev * dev)199 static void __init pci_fixup_cy82c693(struct pci_dev *dev)
200 {
201 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
202 u32 base0, base1;
203
204 if (dev->class & 0x80) { /* primary */
205 base0 = 0x1f0;
206 base1 = 0x3f4;
207 } else { /* secondary */
208 base0 = 0x170;
209 base1 = 0x374;
210 }
211
212 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
213 base0 | PCI_BASE_ADDRESS_SPACE_IO);
214 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
215 base1 | PCI_BASE_ADDRESS_SPACE_IO);
216
217 dev->resource[0].start = 0;
218 dev->resource[0].end = 0;
219 dev->resource[0].flags = 0;
220
221 dev->resource[1].start = 0;
222 dev->resource[1].end = 0;
223 dev->resource[1].flags = 0;
224 } else if (PCI_FUNC(dev->devfn) == 0) {
225 /*
226 * Setup IDE IRQ routing.
227 */
228 pci_write_config_byte(dev, 0x4b, 14);
229 pci_write_config_byte(dev, 0x4c, 15);
230
231 /*
232 * Disable FREQACK handshake, enable USB.
233 */
234 pci_write_config_byte(dev, 0x4d, 0x41);
235
236 /*
237 * Enable PCI retry, and PCI post-write buffer.
238 */
239 pci_write_config_byte(dev, 0x44, 0x17);
240
241 /*
242 * Enable ISA master and DMA post write buffering.
243 */
244 pci_write_config_byte(dev, 0x45, 0x03);
245 }
246 }
247
248 struct pci_fixup pcibios_fixups[] = {
249 {
250 PCI_FIXUP_HEADER,
251 PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693,
252 pci_fixup_cy82c693
253 }, {
254 PCI_FIXUP_HEADER,
255 PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
256 pci_fixup_dec21142
257 }, {
258 PCI_FIXUP_HEADER,
259 PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285,
260 pci_fixup_dec21285
261 }, {
262 PCI_FIXUP_HEADER,
263 PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553,
264 pci_fixup_83c553
265 }, {
266 PCI_FIXUP_HEADER,
267 PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F,
268 pci_fixup_unassign
269 }, {
270 PCI_FIXUP_HEADER,
271 PCI_ANY_ID, PCI_ANY_ID,
272 pci_fixup_ide_bases
273 }, { 0 }
274 };
275
276 void __init
pcibios_update_resource(struct pci_dev * dev,struct resource * root,struct resource * res,int resource)277 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
278 struct resource *res, int resource)
279 {
280 struct pci_sys_data *sys = dev->sysdata;
281 u32 val, check;
282 int reg;
283
284 if (debug_pci)
285 printk("PCI: Assigning %3s %08lx to %s\n",
286 res->flags & IORESOURCE_IO ? "IO" : "MEM",
287 res->start, dev->name);
288
289 if (resource < 6) {
290 reg = PCI_BASE_ADDRESS_0 + 4*resource;
291 } else if (resource == PCI_ROM_RESOURCE) {
292 reg = dev->rom_base_reg;
293 } else {
294 /* Somebody might have asked allocation of a
295 * non-standard resource.
296 */
297 return;
298 }
299
300 val = res->start;
301 if (res->flags & IORESOURCE_MEM)
302 val -= sys->mem_offset;
303 val |= res->flags & PCI_REGION_FLAG_MASK;
304
305 pci_write_config_dword(dev, reg, val);
306 pci_read_config_dword(dev, reg, &check);
307 if ((val ^ check) & ((val & PCI_BASE_ADDRESS_SPACE_IO) ?
308 PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
309 printk(KERN_ERR "PCI: Error while updating region "
310 "%s/%d (%08x != %08x)\n", dev->slot_name,
311 resource, val, check);
312 }
313 }
314
pcibios_update_irq(struct pci_dev * dev,int irq)315 void __init pcibios_update_irq(struct pci_dev *dev, int irq)
316 {
317 if (debug_pci)
318 printk("PCI: Assigning IRQ %02d to %s\n", irq, dev->name);
319 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
320 }
321
322 /*
323 * If the bus contains any of these devices, then we must not turn on
324 * parity checking of any kind. Currently this is CyberPro 20x0 only.
325 */
pdev_bad_for_parity(struct pci_dev * dev)326 static inline int pdev_bad_for_parity(struct pci_dev *dev)
327 {
328 return (dev->vendor == PCI_VENDOR_ID_INTERG &&
329 (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
330 dev->device == PCI_DEVICE_ID_INTERG_2010));
331 }
332
333 /*
334 * Adjust the device resources from bus-centric to Linux-centric.
335 */
336 static void __init
pdev_fixup_device_resources(struct pci_sys_data * root,struct pci_dev * dev)337 pdev_fixup_device_resources(struct pci_sys_data *root, struct pci_dev *dev)
338 {
339 int i;
340
341 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
342 if (dev->resource[i].start == 0)
343 continue;
344 if (dev->resource[i].flags & IORESOURCE_MEM) {
345 dev->resource[i].start += root->mem_offset;
346 dev->resource[i].end += root->mem_offset;
347 }
348 }
349 }
350
351 static void __init
pbus_assign_bus_resources(struct pci_bus * bus,struct pci_sys_data * root)352 pbus_assign_bus_resources(struct pci_bus *bus, struct pci_sys_data *root)
353 {
354 struct pci_dev *dev = bus->self;
355 int i;
356
357 if (!dev) {
358 /*
359 * Assign root bus resources.
360 */
361 for (i = 0; i < 3; i++)
362 bus->resource[i] = root->resource[i];
363 }
364 }
365
366 /*
367 * pcibios_fixup_bus - Called after each bus is probed,
368 * but before its children are examined.
369 */
pcibios_fixup_bus(struct pci_bus * bus)370 void __init pcibios_fixup_bus(struct pci_bus *bus)
371 {
372 struct pci_sys_data *root = bus->sysdata;
373 struct list_head *walk;
374 u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
375 u16 all_status = -1;
376
377 pbus_assign_bus_resources(bus, root);
378
379 /*
380 * Walk the devices on this bus, working out what we can
381 * and can't support.
382 */
383 for (walk = bus->devices.next; walk != &bus->devices; walk = walk->next) {
384 struct pci_dev *dev = pci_dev_b(walk);
385 u16 status;
386
387 pdev_fixup_device_resources(root, dev);
388
389 pci_read_config_word(dev, PCI_STATUS, &status);
390 all_status &= status;
391
392 if (pdev_bad_for_parity(dev))
393 features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
394
395 /*
396 * If this device is an ISA bridge, set the have_isa_bridge
397 * flag. We will then go looking for things like keyboard,
398 * etc
399 */
400 if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA ||
401 dev->class >> 8 == PCI_CLASS_BRIDGE_EISA)
402 have_isa_bridge = !0;
403 }
404
405 /*
406 * If any device on this bus does not support fast back to back
407 * transfers, then the bus as a whole is not able to support them.
408 * Having fast back to back transfers on saves us one PCI cycle
409 * per transaction.
410 */
411 if (all_status & PCI_STATUS_FAST_BACK)
412 features |= PCI_COMMAND_FAST_BACK;
413
414 /*
415 * Now walk the devices again, this time setting them up.
416 */
417 for (walk = bus->devices.next; walk != &bus->devices; walk = walk->next) {
418 struct pci_dev *dev = pci_dev_b(walk);
419 u16 cmd;
420
421 pci_read_config_word(dev, PCI_COMMAND, &cmd);
422 cmd |= features;
423 pci_write_config_word(dev, PCI_COMMAND, cmd);
424 }
425
426 /*
427 * Report what we did for this bus
428 */
429 printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n",
430 bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
431 }
432
433 /*
434 * Convert from Linux-centric to bus-centric addresses for bridge devices.
435 */
436 void __init
pcibios_fixup_pbus_ranges(struct pci_bus * bus,struct pbus_set_ranges_data * ranges)437 pcibios_fixup_pbus_ranges(struct pci_bus *bus, struct pbus_set_ranges_data *ranges)
438 {
439 struct pci_sys_data *root = bus->sysdata;
440
441 ranges->mem_start -= root->mem_offset;
442 ranges->mem_end -= root->mem_offset;
443 ranges->prefetch_start -= root->mem_offset;
444 ranges->prefetch_end -= root->mem_offset;
445 }
446
no_swizzle(struct pci_dev * dev,u8 * pin)447 u8 __init no_swizzle(struct pci_dev *dev, u8 *pin)
448 {
449 return 0;
450 }
451
452 extern struct hw_pci ebsa285_pci;
453 extern struct hw_pci cats_pci;
454 extern struct hw_pci netwinder_pci;
455 extern struct hw_pci personal_server_pci;
456 extern struct hw_pci ftv_pci;
457 extern struct hw_pci shark_pci;
458 extern struct hw_pci integrator_pci;
459
pcibios_init(void)460 void __init pcibios_init(void)
461 {
462 struct pci_sys_data *root;
463 struct hw_pci *hw = NULL;
464
465 do {
466 #ifdef CONFIG_ARCH_EBSA285
467 if (machine_is_ebsa285()) {
468 hw = &ebsa285_pci;
469 break;
470 }
471 #endif
472 #ifdef CONFIG_ARCH_SHARK
473 if (machine_is_shark()) {
474 hw = &shark_pci;
475 break;
476 }
477 #endif
478 #ifdef CONFIG_ARCH_CATS
479 if (machine_is_cats()) {
480 hw = &cats_pci;
481 break;
482 }
483 #endif
484 #ifdef CONFIG_ARCH_NETWINDER
485 if (machine_is_netwinder()) {
486 hw = &netwinder_pci;
487 break;
488 }
489 #endif
490 #ifdef CONFIG_ARCH_PERSONAL_SERVER
491 if (machine_is_personal_server()) {
492 hw = &personal_server_pci;
493 break;
494 }
495 #endif
496 #ifdef CONFIG_ARCH_FTVPCI
497 if (machine_is_ftvpci()) {
498 hw = &ftv_pci;
499 break;
500 }
501 #endif
502 #ifdef CONFIG_ARCH_INTEGRATOR
503 if (machine_is_integrator()) {
504 hw = &integrator_pci;
505 break;
506 }
507 #endif
508 } while (0);
509
510 if (hw == NULL)
511 return;
512
513 root = kmalloc(sizeof(*root), GFP_KERNEL);
514 if (!root)
515 panic("PCI: unable to allocate root data!");
516
517 root->hw = hw;
518 root->mem_offset = hw->mem_offset;
519
520 memset(root->resource, 0, sizeof(root->resource));
521
522 /*
523 * Setup the resources for this bus.
524 * resource[0] - IO ports
525 * resource[1] - non-prefetchable memory
526 * resource[2] - prefetchable memory
527 */
528 if (root->hw->setup_resources)
529 root->hw->setup_resources(root->resource);
530 else {
531 root->resource[0] = &ioport_resource;
532 root->resource[1] = &iomem_resource;
533 root->resource[2] = NULL;
534 }
535
536 /*
537 * Set up the host bridge, and scan the bus.
538 */
539 root->hw->init(root);
540
541 /*
542 * Assign any unassigned resources.
543 */
544 pci_assign_unassigned_resources();
545 pci_fixup_irqs(root->hw->swizzle, root->hw->map_irq);
546 }
547
pcibios_setup(char * str)548 char * __init pcibios_setup(char *str)
549 {
550 if (!strcmp(str, "debug")) {
551 debug_pci = 1;
552 return NULL;
553 }
554 return str;
555 }
556
557 /*
558 * From arch/i386/kernel/pci-i386.c:
559 *
560 * We need to avoid collisions with `mirrored' VGA ports
561 * and other strange ISA hardware, so we always want the
562 * addresses to be allocated in the 0x000-0x0ff region
563 * modulo 0x400.
564 *
565 * Why? Because some silly external IO cards only decode
566 * the low 10 bits of the IO address. The 0x00-0xff region
567 * is reserved for motherboard devices that decode all 16
568 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
569 * but we want to try to avoid allocating at 0x2900-0x2bff
570 * which might be mirrored at 0x0100-0x03ff..
571 */
pcibios_align_resource(void * data,struct resource * res,unsigned long size,unsigned long align)572 void pcibios_align_resource(void *data, struct resource *res,
573 unsigned long size, unsigned long align)
574 {
575 if (res->flags & IORESOURCE_IO) {
576 unsigned long start = res->start;
577
578 if (start & 0x300)
579 res->start = (start + 0x3ff) & ~0x3ff;
580 }
581 }
582
583 /**
584 * pcibios_enable_device - Enable I/O and memory.
585 * @dev: PCI device to be enabled
586 */
pcibios_enable_device(struct pci_dev * dev,int mask)587 int pcibios_enable_device(struct pci_dev *dev, int mask)
588 {
589 u16 cmd, old_cmd;
590 int idx;
591 struct resource *r;
592
593 pci_read_config_word(dev, PCI_COMMAND, &cmd);
594 old_cmd = cmd;
595 for (idx = 0; idx < 6; idx++) {
596 /* Only set up the requested stuff */
597 if (!(mask & (1 << idx)))
598 continue;
599
600 r = dev->resource + idx;
601 if (!r->start && r->end) {
602 printk(KERN_ERR "PCI: Device %s not available because"
603 " of resource collisions\n", dev->slot_name);
604 return -EINVAL;
605 }
606 if (r->flags & IORESOURCE_IO)
607 cmd |= PCI_COMMAND_IO;
608 if (r->flags & IORESOURCE_MEM)
609 cmd |= PCI_COMMAND_MEMORY;
610 }
611
612 /*
613 * Bridges (eg, cardbus bridges) need to be fully enabled
614 */
615 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
616 cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
617
618 if (cmd != old_cmd) {
619 printk("PCI: enabling device %s (%04x -> %04x)\n",
620 dev->slot_name, old_cmd, cmd);
621 pci_write_config_word(dev, PCI_COMMAND, cmd);
622 }
623 return 0;
624 }
625