1/* Optimized version of the standard memset() function. 2 This file is part of the GNU C Library. 3 Copyright (C) 2000-2022 Free Software Foundation, Inc. 4 5 The GNU C Library is free software; you can redistribute it and/or 6 modify it under the terms of the GNU Lesser General Public 7 License as published by the Free Software Foundation; either 8 version 2.1 of the License, or (at your option) any later version. 9 10 The GNU C Library is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 Lesser General Public License for more details. 14 15 You should have received a copy of the GNU Lesser General Public 16 License along with the GNU C Library; if not, see 17 <https://www.gnu.org/licenses/>. */ 18 19/* Return: dest 20 21 Inputs: 22 in0: dest 23 in1: value 24 in2: count 25 26 The algorithm is fairly straightforward: set byte by byte until we 27 we get to a 16B-aligned address, then loop on 128 B chunks using an 28 early store as prefetching, then loop on 32B chucks, then clear remaining 29 words, finally clear remaining bytes. 30 Since a stf.spill f0 can store 16B in one go, we use this instruction 31 to get peak speed when value = 0. */ 32 33#include <sysdep.h> 34#undef ret 35 36#define dest in0 37#define value in1 38#define cnt in2 39 40#define tmp r31 41#define save_lc r30 42#define ptr0 r29 43#define ptr1 r28 44#define ptr2 r27 45#define ptr3 r26 46#define ptr9 r24 47#define loopcnt r23 48#define linecnt r22 49#define bytecnt r21 50 51#define fvalue f6 52 53// This routine uses only scratch predicate registers (p6 - p15) 54#define p_scr p6 // default register for same-cycle branches 55#define p_nz p7 56#define p_zr p8 57#define p_unalgn p9 58#define p_y p11 59#define p_n p12 60#define p_yy p13 61#define p_nn p14 62 63#define movi0 mov 64 65#define MIN1 15 66#define MIN1P1HALF 8 67#define LINE_SIZE 128 68#define LSIZE_SH 7 // shift amount 69#define PREF_AHEAD 8 70 71#define USE_FLP 72#if defined(USE_INT) 73#define store st8 74#define myval value 75#elif defined(USE_FLP) 76#define store stf8 77#define myval fvalue 78#endif 79 80.align 64 81ENTRY(memset) 82{ .mmi 83 .prologue 84 alloc tmp = ar.pfs, 3, 0, 0, 0 85 lfetch.nt1 [dest] 86 .save ar.lc, save_lc 87 movi0 save_lc = ar.lc 88} { .mmi 89 .body 90 mov ret0 = dest // return value 91 cmp.ne p_nz, p_zr = value, r0 // use stf.spill if value is zero 92 cmp.eq p_scr, p0 = cnt, r0 93;; } 94{ .mmi 95 and ptr2 = -(MIN1+1), dest // aligned address 96 and tmp = MIN1, dest // prepare to check for alignment 97 tbit.nz p_y, p_n = dest, 0 // Do we have an odd address? (M_B_U) 98} { .mib 99 mov ptr1 = dest 100 mux1 value = value, @brcst // create 8 identical bytes in word 101(p_scr) br.ret.dpnt.many rp // return immediately if count = 0 102;; } 103{ .mib 104 cmp.ne p_unalgn, p0 = tmp, r0 105} { .mib // NB: # of bytes to move is 1 higher 106 sub bytecnt = (MIN1+1), tmp // than loopcnt 107 cmp.gt p_scr, p0 = 16, cnt // is it a minimalistic task? 108(p_scr) br.cond.dptk.many .move_bytes_unaligned // go move just a few (M_B_U) 109;; } 110{ .mmi 111(p_unalgn) add ptr1 = (MIN1+1), ptr2 // after alignment 112(p_unalgn) add ptr2 = MIN1P1HALF, ptr2 // after alignment 113(p_unalgn) tbit.nz.unc p_y, p_n = bytecnt, 3 // should we do a st8 ? 114;; } 115{ .mib 116(p_y) add cnt = -8, cnt 117(p_unalgn) tbit.nz.unc p_yy, p_nn = bytecnt, 2 // should we do a st4 ? 118} { .mib 119(p_y) st8 [ptr2] = value, -4 120(p_n) add ptr2 = 4, ptr2 121;; } 122{ .mib 123(p_yy) add cnt = -4, cnt 124(p_unalgn) tbit.nz.unc p_y, p_n = bytecnt, 1 // should we do a st2 ? 125} { .mib 126(p_yy) st4 [ptr2] = value, -2 127(p_nn) add ptr2 = 2, ptr2 128;; } 129{ .mmi 130 mov tmp = LINE_SIZE+1 // for compare 131(p_y) add cnt = -2, cnt 132(p_unalgn) tbit.nz.unc p_yy, p_nn = bytecnt, 0 // should we do a st1 ? 133} { .mmi 134 setf.sig fvalue=value // transfer value to FLP side 135(p_y) st2 [ptr2] = value, -1 136(p_n) add ptr2 = 1, ptr2 137;; } 138 139{ .mmi 140(p_yy) st1 [ptr2] = value 141 cmp.gt p_scr, p0 = tmp, cnt // is it a minimalistic task? 142} { .mbb 143(p_yy) add cnt = -1, cnt 144(p_scr) br.cond.dpnt.many .fraction_of_line // go move just a few 145;; } 146 147{ .mib 148 nop.m 0 149 shr.u linecnt = cnt, LSIZE_SH 150(p_zr) br.cond.dptk.many .l1b // Jump to use stf.spill 151;; } 152 153#ifndef GAS_ALIGN_BREAKS_UNWIND_INFO 154 .align 32 // -------- // L1A: store ahead into cache lines; fill later 155#endif 156{ .mmi 157 and tmp = -(LINE_SIZE), cnt // compute end of range 158 mov ptr9 = ptr1 // used for prefetching 159 and cnt = (LINE_SIZE-1), cnt // remainder 160} { .mmi 161 mov loopcnt = PREF_AHEAD-1 // default prefetch loop 162 cmp.gt p_scr, p0 = PREF_AHEAD, linecnt // check against actual value 163;; } 164{ .mmi 165(p_scr) add loopcnt = -1, linecnt // start of stores 166 add ptr2 = 8, ptr1 // (beyond prefetch stores) 167 add ptr1 = tmp, ptr1 // first address beyond total 168;; } // range 169{ .mmi 170 add tmp = -1, linecnt // next loop count 171 movi0 ar.lc = loopcnt 172;; } 173.pref_l1a: 174{ .mib 175 store [ptr9] = myval, 128 // Do stores one cache line apart 176 nop.i 0 177 br.cloop.dptk.few .pref_l1a 178;; } 179{ .mmi 180 add ptr0 = 16, ptr2 // Two stores in parallel 181 movi0 ar.lc = tmp 182;; } 183.l1ax: 184 { .mmi 185 store [ptr2] = myval, 8 186 store [ptr0] = myval, 8 187 ;; } 188 { .mmi 189 store [ptr2] = myval, 24 190 store [ptr0] = myval, 24 191 ;; } 192 { .mmi 193 store [ptr2] = myval, 8 194 store [ptr0] = myval, 8 195 ;; } 196 { .mmi 197 store [ptr2] = myval, 24 198 store [ptr0] = myval, 24 199 ;; } 200 { .mmi 201 store [ptr2] = myval, 8 202 store [ptr0] = myval, 8 203 ;; } 204 { .mmi 205 store [ptr2] = myval, 24 206 store [ptr0] = myval, 24 207 ;; } 208 { .mmi 209 store [ptr2] = myval, 8 210 store [ptr0] = myval, 32 211 cmp.lt p_scr, p0 = ptr9, ptr1 // do we need more prefetching? 212 ;; } 213{ .mmb 214 store [ptr2] = myval, 24 215(p_scr) store [ptr9] = myval, 128 216 br.cloop.dptk.few .l1ax 217;; } 218{ .mbb 219 cmp.le p_scr, p0 = 8, cnt // just a few bytes left ? 220(p_scr) br.cond.dpnt.many .fraction_of_line // Branch no. 2 221 br.cond.dpnt.many .move_bytes_from_alignment // Branch no. 3 222;; } 223 224#ifdef GAS_ALIGN_BREAKS_UNWIND_INFO 225 { nop 0 } 226#else 227 .align 32 228#endif 229.l1b: // ------------------ // L1B: store ahead into cache lines; fill later 230{ .mmi 231 and tmp = -(LINE_SIZE), cnt // compute end of range 232 mov ptr9 = ptr1 // used for prefetching 233 and cnt = (LINE_SIZE-1), cnt // remainder 234} { .mmi 235 mov loopcnt = PREF_AHEAD-1 // default prefetch loop 236 cmp.gt p_scr, p0 = PREF_AHEAD, linecnt // check against actual value 237;; } 238{ .mmi 239(p_scr) add loopcnt = -1, linecnt 240 add ptr2 = 16, ptr1 // start of stores (beyond prefetch stores) 241 add ptr1 = tmp, ptr1 // first address beyond total range 242;; } 243{ .mmi 244 add tmp = -1, linecnt // next loop count 245 movi0 ar.lc = loopcnt 246;; } 247.pref_l1b: 248{ .mib 249 stf.spill [ptr9] = f0, 128 // Do stores one cache line apart 250 nop.i 0 251 br.cloop.dptk.few .pref_l1b 252;; } 253{ .mmi 254 add ptr0 = 16, ptr2 // Two stores in parallel 255 movi0 ar.lc = tmp 256;; } 257.l1bx: 258 { .mmi 259 stf.spill [ptr2] = f0, 32 260 stf.spill [ptr0] = f0, 32 261 ;; } 262 { .mmi 263 stf.spill [ptr2] = f0, 32 264 stf.spill [ptr0] = f0, 32 265 ;; } 266 { .mmi 267 stf.spill [ptr2] = f0, 32 268 stf.spill [ptr0] = f0, 64 269 cmp.lt p_scr, p0 = ptr9, ptr1 // do we need more prefetching? 270 ;; } 271{ .mmb 272 stf.spill [ptr2] = f0, 32 273(p_scr) stf.spill [ptr9] = f0, 128 274 br.cloop.dptk.few .l1bx 275;; } 276{ .mib 277 cmp.gt p_scr, p0 = 8, cnt // just a few bytes left ? 278(p_scr) br.cond.dpnt.many .move_bytes_from_alignment 279;; } 280 281.fraction_of_line: 282{ .mib 283 add ptr2 = 16, ptr1 284 shr.u loopcnt = cnt, 5 // loopcnt = cnt / 32 285;; } 286{ .mib 287 cmp.eq p_scr, p0 = loopcnt, r0 288 add loopcnt = -1, loopcnt 289(p_scr) br.cond.dpnt.many store_words 290;; } 291{ .mib 292 and cnt = 0x1f, cnt // compute the remaining cnt 293 movi0 ar.lc = loopcnt 294;; } 295#ifndef GAS_ALIGN_BREAKS_UNWIND_INFO 296 .align 32 297#endif 298.l2: // ---------------------------- // L2A: store 32B in 2 cycles 299{ .mmb 300 store [ptr1] = myval, 8 301 store [ptr2] = myval, 8 302;; } { .mmb 303 store [ptr1] = myval, 24 304 store [ptr2] = myval, 24 305 br.cloop.dptk.many .l2 306;; } 307store_words: 308{ .mib 309 cmp.gt p_scr, p0 = 8, cnt // just a few bytes left ? 310(p_scr) br.cond.dpnt.many .move_bytes_from_alignment // Branch 311;; } 312 313{ .mmi 314 store [ptr1] = myval, 8 // store 315 cmp.le p_y, p_n = 16, cnt // 316 add cnt = -8, cnt // subtract 317;; } 318{ .mmi 319(p_y) store [ptr1] = myval, 8 // store 320(p_y) cmp.le.unc p_yy, p_nn = 16, cnt // 321(p_y) add cnt = -8, cnt // subtract 322;; } 323{ .mmi // store 324(p_yy) store [ptr1] = myval, 8 // 325(p_yy) add cnt = -8, cnt // subtract 326;; } 327 328.move_bytes_from_alignment: 329{ .mib 330 cmp.eq p_scr, p0 = cnt, r0 331 tbit.nz.unc p_y, p0 = cnt, 2 // should we terminate with a st4 ? 332(p_scr) br.cond.dpnt.few .restore_and_exit 333;; } 334{ .mib 335(p_y) st4 [ptr1] = value, 4 336 tbit.nz.unc p_yy, p0 = cnt, 1 // should we terminate with a st2 ? 337;; } 338{ .mib 339(p_yy) st2 [ptr1] = value, 2 340 tbit.nz.unc p_y, p0 = cnt, 0 341;; } 342 343{ .mib 344(p_y) st1 [ptr1] = value 345;; } 346.restore_and_exit: 347{ .mib 348 nop.m 0 349 movi0 ar.lc = save_lc 350 br.ret.sptk.many rp 351;; } 352 353.move_bytes_unaligned: 354{ .mmi 355 .pred.rel "mutex",p_y, p_n 356 .pred.rel "mutex",p_yy, p_nn 357(p_n) cmp.le p_yy, p_nn = 4, cnt 358(p_y) cmp.le p_yy, p_nn = 5, cnt 359(p_n) add ptr2 = 2, ptr1 360} { .mmi 361(p_y) add ptr2 = 3, ptr1 362(p_y) st1 [ptr1] = value, 1 // fill 1 (odd-aligned) byte 363(p_y) add cnt = -1, cnt // [15, 14 (or less) left] 364;; } 365{ .mmi 366(p_yy) cmp.le.unc p_y, p0 = 8, cnt 367 add ptr3 = ptr1, cnt // prepare last store 368 movi0 ar.lc = save_lc 369} { .mmi 370(p_yy) st2 [ptr1] = value, 4 // fill 2 (aligned) bytes 371(p_yy) st2 [ptr2] = value, 4 // fill 2 (aligned) bytes 372(p_yy) add cnt = -4, cnt // [11, 10 (o less) left] 373;; } 374{ .mmi 375(p_y) cmp.le.unc p_yy, p0 = 8, cnt 376 add ptr3 = -1, ptr3 // last store 377 tbit.nz p_scr, p0 = cnt, 1 // will there be a st2 at the end ? 378} { .mmi 379(p_y) st2 [ptr1] = value, 4 // fill 2 (aligned) bytes 380(p_y) st2 [ptr2] = value, 4 // fill 2 (aligned) bytes 381(p_y) add cnt = -4, cnt // [7, 6 (or less) left] 382;; } 383{ .mmi 384(p_yy) st2 [ptr1] = value, 4 // fill 2 (aligned) bytes 385(p_yy) st2 [ptr2] = value, 4 // fill 2 (aligned) bytes 386 // [3, 2 (or less) left] 387 tbit.nz p_y, p0 = cnt, 0 // will there be a st1 at the end ? 388} { .mmi 389(p_yy) add cnt = -4, cnt 390;; } 391{ .mmb 392(p_scr) st2 [ptr1] = value // fill 2 (aligned) bytes 393(p_y) st1 [ptr3] = value // fill last byte (using ptr3) 394 br.ret.sptk.many rp 395;; } 396END(memset) 397libc_hidden_builtin_def (memset) 398