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/linux-6.1.9/drivers/mtd/nand/
Decc-mtk.c118 static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, in mtk_ecc_wait_idle() argument
121 struct device *dev = ecc->dev; in mtk_ecc_wait_idle()
125 ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, in mtk_ecc_wait_idle()
135 struct mtk_ecc *ecc = id; in mtk_ecc_irq() local
138 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) in mtk_ecc_irq()
141 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); in mtk_ecc_irq()
142 if (dec & ecc->sectors) { in mtk_ecc_irq()
147 readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]); in mtk_ecc_irq()
148 ecc->sectors = 0; in mtk_ecc_irq()
149 complete(&ecc->done); in mtk_ecc_irq()
[all …]
Decc-sw-bch.c26 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_calculate()
30 bch_encode(engine_conf->bch, buf, nand->ecc.ctx.conf.step_size, code); in nand_ecc_sw_bch_calculate()
52 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_correct()
53 unsigned int step_size = nand->ecc.ctx.conf.step_size; in nand_ecc_sw_bch_correct()
84 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_cleanup()
110 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_init()
111 unsigned int eccsize = nand->ecc.ctx.conf.step_size; in nand_ecc_sw_bch_init()
172 struct nand_ecc_props *conf = &nand->ecc.ctx.conf; in nand_ecc_sw_bch_init_ctx()
189 conf->step_size = nand->ecc.user_conf.step_size; in nand_ecc_sw_bch_init_ctx()
190 conf->strength = nand->ecc.user_conf.strength; in nand_ecc_sw_bch_init_ctx()
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Decc.c114 if (!nand->ecc.engine || !nand->ecc.engine->ops->init_ctx) in nand_ecc_init_ctx()
117 return nand->ecc.engine->ops->init_ctx(nand); in nand_ecc_init_ctx()
127 if (nand->ecc.engine && nand->ecc.engine->ops->cleanup_ctx) in nand_ecc_cleanup_ctx()
128 nand->ecc.engine->ops->cleanup_ctx(nand); in nand_ecc_cleanup_ctx()
140 if (!nand->ecc.engine || !nand->ecc.engine->ops->prepare_io_req) in nand_ecc_prepare_io_req()
143 return nand->ecc.engine->ops->prepare_io_req(nand, req); in nand_ecc_prepare_io_req()
155 if (!nand->ecc.engine || !nand->ecc.engine->ops->finish_io_req) in nand_ecc_finish_io_req()
158 return nand->ecc.engine->ops->finish_io_req(nand, req); in nand_ecc_finish_io_req()
167 unsigned int total_ecc_bytes = nand->ecc.ctx.total; in nand_ooblayout_ecc_sp()
213 .ecc = nand_ooblayout_ecc_sp,
[all …]
/linux-6.1.9/drivers/mtd/nand/raw/ingenic/
Dingenic_ecc.c27 int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
31 return ecc->ops->calculate(ecc, params, buf, ecc_code); in ingenic_ecc_calculate()
47 int ingenic_ecc_correct(struct ingenic_ecc *ecc, in ingenic_ecc_correct() argument
51 return ecc->ops->correct(ecc, params, buf, ecc_code); in ingenic_ecc_correct()
68 struct ingenic_ecc *ecc; in ingenic_ecc_get() local
79 ecc = platform_get_drvdata(pdev); in ingenic_ecc_get()
80 clk_prepare_enable(ecc->clk); in ingenic_ecc_get()
82 return ecc; in ingenic_ecc_get()
97 struct ingenic_ecc *ecc = NULL; in of_ingenic_ecc_get() local
110 ecc = ingenic_ecc_get(np); in of_ingenic_ecc_get()
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Dingenic_nand_drv.c45 struct ingenic_ecc *ecc; member
76 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_ecc() local
78 if (section || !ecc->total) in qi_lb60_ooblayout_ecc()
81 oobregion->length = ecc->total; in qi_lb60_ooblayout_ecc()
91 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_free() local
96 oobregion->length = mtd->oobsize - ecc->total - 12; in qi_lb60_ooblayout_free()
97 oobregion->offset = 12 + ecc->total; in qi_lb60_ooblayout_free()
103 .ecc = qi_lb60_ooblayout_ecc,
111 struct nand_ecc_ctrl *ecc = &chip->ecc; in jz4725b_ooblayout_ecc() local
113 if (section || !ecc->total) in jz4725b_ooblayout_ecc()
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Djz4740_ecc.c45 static void jz4740_ecc_reset(struct ingenic_ecc *ecc, bool calc_ecc) in jz4740_ecc_reset() argument
50 writel(0, ecc->base + JZ_REG_NAND_IRQ_STAT); in jz4740_ecc_reset()
53 reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); in jz4740_ecc_reset()
62 writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); in jz4740_ecc_reset()
65 static int jz4740_ecc_calculate(struct ingenic_ecc *ecc, in jz4740_ecc_calculate() argument
73 jz4740_ecc_reset(ecc, true); in jz4740_ecc_calculate()
76 status = readl(ecc->base + JZ_REG_NAND_IRQ_STAT); in jz4740_ecc_calculate()
82 reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); in jz4740_ecc_calculate()
84 writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); in jz4740_ecc_calculate()
87 ecc_code[i] = readb(ecc->base + JZ_REG_NAND_PAR0 + i); in jz4740_ecc_calculate()
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Dingenic_ecc.h29 int ingenic_ecc_calculate(struct ingenic_ecc *ecc,
32 int ingenic_ecc_correct(struct ingenic_ecc *ecc,
36 void ingenic_ecc_release(struct ingenic_ecc *ecc);
39 int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
46 int ingenic_ecc_correct(struct ingenic_ecc *ecc, in ingenic_ecc_correct() argument
53 void ingenic_ecc_release(struct ingenic_ecc *ecc) in ingenic_ecc_release() argument
64 void (*disable)(struct ingenic_ecc *ecc);
65 int (*calculate)(struct ingenic_ecc *ecc,
68 int (*correct)(struct ingenic_ecc *ecc,
/linux-6.1.9/drivers/dma/ti/
Dedma.c220 struct edma_cc *ecc; member
301 static inline unsigned int edma_read(struct edma_cc *ecc, int offset) in edma_read() argument
303 return (unsigned int)__raw_readl(ecc->base + offset); in edma_read()
306 static inline void edma_write(struct edma_cc *ecc, int offset, int val) in edma_write() argument
308 __raw_writel(val, ecc->base + offset); in edma_write()
311 static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and, in edma_modify() argument
314 unsigned val = edma_read(ecc, offset); in edma_modify()
318 edma_write(ecc, offset, val); in edma_modify()
321 static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and) in edma_and() argument
323 unsigned val = edma_read(ecc, offset); in edma_and()
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/linux-6.1.9/Documentation/devicetree/bindings/edac/
Dsocfpga-eccmgr.txt8 - compatible : Should be "altr,socfpga-ecc-manager"
17 - compatible : Should be "altr,socfpga-l2-ecc"
24 - compatible : Should be "altr,socfpga-ocram-ecc"
33 compatible = "altr,socfpga-ecc-manager";
38 l2-ecc@ffd08140 {
39 compatible = "altr,socfpga-l2-ecc";
44 ocram-ecc@ffd08144 {
45 compatible = "altr,socfpga-ocram-ecc";
58 - compatible : Should be "altr,socfpga-a10-ecc-manager"
73 - compatible : Should be "altr,socfpga-a10-l2-ecc"
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/linux-6.1.9/drivers/mtd/nand/raw/
Dnand_base.c263 res = chip->ecc.read_oob(chip, first_page + page_offset); in nand_block_bad()
476 status = chip->ecc.write_oob_raw(chip, page & chip->pagemask); in nand_do_write_oob()
478 status = chip->ecc.write_oob(chip, page & chip->pagemask); in nand_do_write_oob()
2750 void *ecc, int ecclen, in nand_check_erased_ecc_chunk() argument
2763 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold); in nand_check_erased_ecc_chunk()
2778 memset(ecc, 0xff, ecclen); in nand_check_erased_ecc_chunk()
2886 int eccsize = chip->ecc.size; in nand_read_page_raw_syndrome()
2887 int eccbytes = chip->ecc.bytes; in nand_read_page_raw_syndrome()
2895 for (steps = chip->ecc.steps; steps > 0; steps--) { in nand_read_page_raw_syndrome()
2902 if (chip->ecc.prepad) { in nand_read_page_raw_syndrome()
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Dnand_micron.c66 struct micron_on_die_ecc ecc; member
127 .ecc = micron_nand_on_die_4_ooblayout_ecc,
140 oobregion->offset = mtd->oobsize - chip->ecc.total; in micron_nand_on_die_8_ooblayout_ecc()
141 oobregion->length = chip->ecc.total; in micron_nand_on_die_8_ooblayout_ecc()
156 oobregion->length = mtd->oobsize - chip->ecc.total - 2; in micron_nand_on_die_8_ooblayout_free()
162 .ecc = micron_nand_on_die_8_ooblayout_ecc,
172 if (micron->ecc.forced) in micron_nand_on_die_ecc_setup()
175 if (micron->ecc.enabled == enable) in micron_nand_on_die_ecc_setup()
183 micron->ecc.enabled = enable; in micron_nand_on_die_ecc_setup()
242 ret = nand_read_page_op(chip, page, 0, micron->ecc.rawbuf, in micron_nand_on_die_ecc_status_4()
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Dsunxi_nand.c196 struct sunxi_nand_hw_ecc *ecc; member
604 bool ecc) in sunxi_nfc_randomizer_state() argument
613 if (ecc) { in sunxi_nfc_randomizer_state()
624 bool ecc) in sunxi_nfc_randomizer_config() argument
634 state = sunxi_nfc_randomizer_state(nand, page, ecc); in sunxi_nfc_randomizer_config()
671 bool ecc, int page) in sunxi_nfc_randomizer_write_buf() argument
673 sunxi_nfc_randomizer_config(nand, page, ecc); in sunxi_nfc_randomizer_write_buf()
680 int len, bool ecc, int page) in sunxi_nfc_randomizer_read_buf() argument
682 sunxi_nfc_randomizer_config(nand, page, ecc); in sunxi_nfc_randomizer_read_buf()
697 ecc_ctl |= NFC_ECC_EN | NFC_ECC_MODE(sunxi_nand->ecc->mode) | in sunxi_nfc_hw_ecc_enable()
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Dfsmc_nand.c172 if (section >= chip->ecc.steps) in fsmc_ecc1_ooblayout_ecc()
186 if (section >= chip->ecc.steps) in fsmc_ecc1_ooblayout_free()
191 if (section < chip->ecc.steps - 1) in fsmc_ecc1_ooblayout_free()
200 .ecc = fsmc_ecc1_ooblayout_ecc,
215 if (section >= chip->ecc.steps) in fsmc_ecc4_ooblayout_ecc()
218 oobregion->length = chip->ecc.bytes; in fsmc_ecc4_ooblayout_ecc()
233 if (section >= chip->ecc.steps) in fsmc_ecc4_ooblayout_free()
238 if (section < chip->ecc.steps - 1) in fsmc_ecc4_ooblayout_free()
247 .ecc = fsmc_ecc4_ooblayout_ecc,
392 u8 *ecc) in fsmc_read_hwecc_ecc4() argument
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Domap2.c792 if (info->nand.ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST && in omap_correct_data()
793 info->nand.ecc.size == 2048) in omap_correct_data()
861 val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) | in omap_enable_hwecc()
916 nsectors = chip->ecc.steps; in omap_enable_hwecc_bch()
936 nsectors = chip->ecc.steps; in omap_enable_hwecc_bch()
949 nsectors = chip->ecc.steps; in omap_enable_hwecc_bch()
1005 int eccbytes = info->nand.ecc.bytes; in _omap_calculate_ecc_bch()
1147 int eccbytes = info->nand.ecc.bytes; in omap_calculate_ecc_bch_multi()
1178 for (i = 0; i < info->nand.ecc.size; i++) { in erased_sector_bitflips()
1180 if (flip_bits > info->nand.ecc.strength) in erased_sector_bitflips()
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Drockchip-nand-controller.c198 return (u8 *)p + i * chip->ecc.size; in rk_nfc_buf_to_data_ptr()
215 poi = chip->oob_poi + rknand->metadata_size + chip->ecc.bytes * i; in rk_nfc_buf_to_oob_ecc_ptr()
222 return chip->ecc.size + chip->ecc.bytes + NFC_SYS_DATA_SIZE; in rk_nfc_data_len()
236 return nfc->page_buf + i * rk_nfc_data_len(chip) + chip->ecc.size; in rk_nfc_oob_ptr()
266 struct nand_ecc_ctrl *ecc = &chip->ecc; in rk_nfc_select_chip() local
300 if (nfc->cur_ecc != ecc->strength) in rk_nfc_select_chip()
301 rk_nfc_hw_ecc_setup(chip, ecc->strength); in rk_nfc_select_chip()
513 struct nand_ecc_ctrl *ecc = &chip->ecc; in rk_nfc_write_page_raw() local
519 rknand->boot_ecc != ecc->strength) { in rk_nfc_write_page_raw()
530 for (i = 0; i < ecc->steps; i++) { in rk_nfc_write_page_raw()
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Dmtk_nand.c147 struct mtk_ecc *ecc; member
186 return (u8 *)p + i * chip->ecc.size; in data_ptr()
212 return chip->ecc.size + mtk_nand->spare_per_sector; in mtk_data_len()
226 return nfc->buffer + i * mtk_data_len(chip) + chip->ecc.size; in mtk_oob_ptr()
336 if (chip->ecc.size == 512) in mtk_nfc_hw_runtime_config()
342 if (chip->ecc.size == 512) in mtk_nfc_hw_runtime_config()
348 if (chip->ecc.size == 512) in mtk_nfc_hw_runtime_config()
365 if (chip->ecc.size == 1024) in mtk_nfc_hw_runtime_config()
384 nfc->ecc_cfg.strength = chip->ecc.strength; in mtk_nfc_hw_runtime_config()
385 nfc->ecc_cfg.len = chip->ecc.size + mtk_nand->fdm.ecc_size; in mtk_nfc_hw_runtime_config()
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Dqcom_nandc.c735 static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw) in qcom_nandc_is_last_cw() argument
737 return cw == (ecc->steps - 1); in qcom_nandc_is_last_cw()
745 struct nand_ecc_ctrl *ecc = &chip->ecc; in nandc_set_read_loc() local
748 if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw)) in nandc_set_read_loc()
753 if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw)) in nandc_set_read_loc()
1210 struct nand_ecc_ctrl *ecc = &chip->ecc; in config_nand_cw_read() local
1214 if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw)) in config_nand_cw_read()
1533 struct nand_ecc_ctrl *ecc = &chip->ecc; in parse_erase_write_errors() local
1537 num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1; in parse_erase_write_errors()
1583 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_command() local
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Dstm32_fmc2_nand.c317 if (chip->ecc.strength == FMC2_ECC_BCH8) { in stm32_fmc2_nfc_setup()
320 } else if (chip->ecc.strength == FMC2_ECC_BCH4) { in stm32_fmc2_nfc_setup()
379 dma_cfg.src_addr += chip->ecc.strength == FMC2_ECC_HAM ? in stm32_fmc2_nfc_select_chip()
390 nfc->dma_ecc_len = chip->ecc.strength == FMC2_ECC_HAM ? in stm32_fmc2_nfc_select_chip()
468 if (chip->ecc.strength != FMC2_ECC_HAM) { in stm32_fmc2_nfc_hwctl()
485 static void stm32_fmc2_nfc_ham_set_ecc(const u32 ecc_sta, u8 *ecc) in stm32_fmc2_nfc_ham_set_ecc() argument
487 ecc[0] = ecc_sta; in stm32_fmc2_nfc_ham_set_ecc()
488 ecc[1] = ecc_sta >> 8; in stm32_fmc2_nfc_ham_set_ecc()
489 ecc[2] = ecc_sta >> 16; in stm32_fmc2_nfc_ham_set_ecc()
493 u8 *ecc) in stm32_fmc2_nfc_ham_calculate() argument
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Dlpc32xx_slc.c168 .ecc = lpc32xx_ooblayout_ecc,
406 static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count) in lpc32xx_slc_ecc_copy() argument
411 uint32_t ce = ecc[i / 3]; in lpc32xx_slc_ecc_copy()
530 for (i = 0; i < chip->ecc.steps; i++) { in lpc32xx_xfer()
533 dma_buf + i * chip->ecc.size, in lpc32xx_xfer()
534 mtd->writesize / chip->ecc.steps, dir); in lpc32xx_xfer()
539 if (i == chip->ecc.steps - 1) in lpc32xx_xfer()
571 host->ecc_buf[chip->ecc.steps - 1] = in lpc32xx_xfer()
614 status = lpc32xx_xfer(mtd, buf, chip->ecc.steps, 1); in lpc32xx_nand_read_page_syndrome()
620 lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps); in lpc32xx_nand_read_page_syndrome()
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Dtegra_nand.c185 struct mtd_oob_region ecc; member
207 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
214 oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4); in tegra_nand_ooblayout_rs_ecc()
226 .ecc = tegra_nand_ooblayout_rs_ecc,
234 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_BCH * chip->ecc.strength, in tegra_nand_ooblayout_bch_ecc()
241 oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4); in tegra_nand_ooblayout_bch_ecc()
247 .ecc = tegra_nand_ooblayout_bch_ecc,
485 if (chip->ecc.algo == NAND_ECC_ALGO_BCH && enable) in tegra_nand_hw_ecc()
710 if (fail_sec_flag ^ GENMASK(chip->ecc.steps - 1, 0)) { in tegra_nand_read_page_hwecc()
726 for_each_set_bit(bit, &fail_sec_flag, chip->ecc.steps) { in tegra_nand_read_page_hwecc()
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/linux-6.1.9/drivers/mtd/nand/raw/atmel/
Dpmecc.c226 if (req->ecc.sectorsize == 512) { in atmel_pmecc_create_gf_tables()
260 if (req->ecc.sectorsize == 512) in atmel_pmecc_get_gf_tables()
282 if (req->pagesize <= 0 || req->oobsize <= 0 || req->ecc.bytes <= 0) in atmel_pmecc_prepare_user_req()
285 if (req->ecc.ooboffset >= 0 && in atmel_pmecc_prepare_user_req()
286 req->ecc.ooboffset + req->ecc.bytes > req->oobsize) in atmel_pmecc_prepare_user_req()
289 if (req->ecc.sectorsize == ATMEL_PMECC_SECTOR_SIZE_AUTO) { in atmel_pmecc_prepare_user_req()
290 if (req->ecc.strength != ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH) in atmel_pmecc_prepare_user_req()
294 req->ecc.sectorsize = 1024; in atmel_pmecc_prepare_user_req()
296 req->ecc.sectorsize = 512; in atmel_pmecc_prepare_user_req()
299 if (req->ecc.sectorsize != 512 && req->ecc.sectorsize != 1024) in atmel_pmecc_prepare_user_req()
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/linux-6.1.9/Documentation/devicetree/bindings/mtd/
Dmtk-nand.txt23 - ecc-engine: Required ECC Engine node.
36 ecc-engine = <&bch>;
49 - nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
50 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
55 - nand-ecc-strength: Number of bits to correct per ECC step.
65 E : nand-ecc-strength.
71 Q : nand-ecc-step-size.
75 this number depends on max ecc step size
77 If max ecc step size supported is 1024,
79 ecc step size is 512, then it should be
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Dhisi504-nand.txt11 - nand-ecc-mode: Support none and hw ecc mode.
17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
22 - nand-ecc-strength = <16>, nand-ecc-step-size = <1024>
34 nand-ecc-mode = "hw";
35 nand-ecc-strength = <16>;
36 nand-ecc-step-size = <1024>;
Dmxicy,nand-ecc-engine.yaml4 $id: http://devicetree.org/schemas/mtd/mxicy,nand-ecc-engine.yaml#
14 const: mxicy,nand-ecc-engine-rev3
46 nand-ecc-engine = <&ecc_engine0>;
50 ecc_engine0: ecc@43c40000 {
51 compatible = "mxicy,nand-ecc-engine-rev3";
65 nand-ecc-engine = <&ecc_engine1>;
70 nand-ecc-engine = <&spi_controller1>;
74 ecc_engine1: ecc@43c40000 {
75 compatible = "mxicy,nand-ecc-engine-rev3";
/linux-6.1.9/fs/ocfs2/
Dblockcheck.c353 u32 ecc; in ocfs2_block_check_compute() local
358 ecc = ocfs2_hamming_encode_block(data, blocksize); in ocfs2_block_check_compute()
364 BUG_ON(ecc > USHRT_MAX); in ocfs2_block_check_compute()
367 bc->bc_ecc = cpu_to_le16((u16)ecc); in ocfs2_block_check_compute()
385 u32 crc, ecc; in ocfs2_block_check_validate() local
405 ecc = ocfs2_hamming_encode_block(data, blocksize); in ocfs2_block_check_validate()
406 ocfs2_hamming_fix_block(data, blocksize, ecc ^ bc_ecc); in ocfs2_block_check_validate()
445 u32 crc, ecc; in ocfs2_block_check_compute_bhs() local
454 for (i = 0, crc = ~0, ecc = 0; i < nr; i++) { in ocfs2_block_check_compute_bhs()
461 ecc = (u16)ocfs2_hamming_encode(ecc, bhs[i]->b_data, in ocfs2_block_check_compute_bhs()
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