Lines Matching refs:ecc
220 struct edma_cc *ecc; member
301 static inline unsigned int edma_read(struct edma_cc *ecc, int offset) in edma_read() argument
303 return (unsigned int)__raw_readl(ecc->base + offset); in edma_read()
306 static inline void edma_write(struct edma_cc *ecc, int offset, int val) in edma_write() argument
308 __raw_writel(val, ecc->base + offset); in edma_write()
311 static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and, in edma_modify() argument
314 unsigned val = edma_read(ecc, offset); in edma_modify()
318 edma_write(ecc, offset, val); in edma_modify()
321 static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and) in edma_and() argument
323 unsigned val = edma_read(ecc, offset); in edma_and()
326 edma_write(ecc, offset, val); in edma_and()
329 static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or) in edma_or() argument
331 unsigned val = edma_read(ecc, offset); in edma_or()
334 edma_write(ecc, offset, val); in edma_or()
337 static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset, in edma_read_array() argument
340 return edma_read(ecc, offset + (i << 2)); in edma_read_array()
343 static inline void edma_write_array(struct edma_cc *ecc, int offset, int i, in edma_write_array() argument
346 edma_write(ecc, offset + (i << 2), val); in edma_write_array()
349 static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i, in edma_modify_array() argument
352 edma_modify(ecc, offset + (i << 2), and, or); in edma_modify_array()
355 static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j, in edma_or_array2() argument
358 edma_or(ecc, offset + ((i * 2 + j) << 2), or); in edma_or_array2()
361 static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i, in edma_write_array2() argument
364 edma_write(ecc, offset + ((i * 2 + j) << 2), val); in edma_write_array2()
367 static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc, in edma_shadow0_read_array() argument
370 return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2)); in edma_shadow0_read_array()
373 static inline void edma_shadow0_write(struct edma_cc *ecc, int offset, in edma_shadow0_write() argument
376 edma_write(ecc, EDMA_SHADOW0 + offset, val); in edma_shadow0_write()
379 static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset, in edma_shadow0_write_array() argument
382 edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val); in edma_shadow0_write_array()
385 static inline void edma_param_modify(struct edma_cc *ecc, int offset, in edma_param_modify() argument
388 edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or); in edma_param_modify()
391 static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no, in edma_assign_priority_to_queue() argument
396 edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit)); in edma_assign_priority_to_queue()
401 struct edma_cc *ecc = echan->ecc; in edma_set_chmap() local
404 if (ecc->chmap_exist) { in edma_set_chmap()
406 edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5)); in edma_set_chmap()
412 struct edma_cc *ecc = echan->ecc; in edma_setup_interrupt() local
418 edma_shadow0_write_array(ecc, SH_ICR, idx, ch_bit); in edma_setup_interrupt()
419 edma_shadow0_write_array(ecc, SH_IESR, idx, ch_bit); in edma_setup_interrupt()
421 edma_shadow0_write_array(ecc, SH_IECR, idx, ch_bit); in edma_setup_interrupt()
428 static void edma_write_slot(struct edma_cc *ecc, unsigned slot, in edma_write_slot() argument
432 if (slot >= ecc->num_slots) in edma_write_slot()
434 memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE); in edma_write_slot()
437 static int edma_read_slot(struct edma_cc *ecc, unsigned slot, in edma_read_slot() argument
441 if (slot >= ecc->num_slots) in edma_read_slot()
443 memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE); in edma_read_slot()
463 static int edma_alloc_slot(struct edma_cc *ecc, int slot) in edma_alloc_slot() argument
468 if (ecc->chmap_exist && slot < ecc->num_channels) in edma_alloc_slot()
473 if (ecc->chmap_exist) in edma_alloc_slot()
476 slot = ecc->num_channels; in edma_alloc_slot()
478 slot = find_next_zero_bit(ecc->slot_inuse, in edma_alloc_slot()
479 ecc->num_slots, in edma_alloc_slot()
481 if (slot == ecc->num_slots) in edma_alloc_slot()
483 if (!test_and_set_bit(slot, ecc->slot_inuse)) in edma_alloc_slot()
486 } else if (slot >= ecc->num_slots) { in edma_alloc_slot()
488 } else if (test_and_set_bit(slot, ecc->slot_inuse)) { in edma_alloc_slot()
492 edma_write_slot(ecc, slot, &dummy_paramset); in edma_alloc_slot()
494 return EDMA_CTLR_CHAN(ecc->id, slot); in edma_alloc_slot()
497 static void edma_free_slot(struct edma_cc *ecc, unsigned slot) in edma_free_slot() argument
500 if (slot >= ecc->num_slots) in edma_free_slot()
503 edma_write_slot(ecc, slot, &dummy_paramset); in edma_free_slot()
504 clear_bit(slot, ecc->slot_inuse); in edma_free_slot()
515 static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to) in edma_link() argument
518 dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n"); in edma_link()
522 if (from >= ecc->num_slots || to >= ecc->num_slots) in edma_link()
525 edma_param_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000, in edma_link()
537 static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot, in edma_get_position() argument
546 return edma_read(ecc, offs); in edma_get_position()
557 struct edma_cc *ecc = echan->ecc; in edma_start() local
564 dev_dbg(ecc->dev, "ESR%d %08x\n", idx, in edma_start()
565 edma_shadow0_read_array(ecc, SH_ESR, idx)); in edma_start()
566 edma_shadow0_write_array(ecc, SH_ESR, idx, ch_bit); in edma_start()
569 dev_dbg(ecc->dev, "ER%d %08x\n", idx, in edma_start()
570 edma_shadow0_read_array(ecc, SH_ER, idx)); in edma_start()
572 edma_write_array(ecc, EDMA_ECR, idx, ch_bit); in edma_start()
573 edma_write_array(ecc, EDMA_EMCR, idx, ch_bit); in edma_start()
575 edma_shadow0_write_array(ecc, SH_SECR, idx, ch_bit); in edma_start()
576 edma_shadow0_write_array(ecc, SH_EESR, idx, ch_bit); in edma_start()
577 dev_dbg(ecc->dev, "EER%d %08x\n", idx, in edma_start()
578 edma_shadow0_read_array(ecc, SH_EER, idx)); in edma_start()
584 struct edma_cc *ecc = echan->ecc; in edma_stop() local
589 edma_shadow0_write_array(ecc, SH_EECR, idx, ch_bit); in edma_stop()
590 edma_shadow0_write_array(ecc, SH_ECR, idx, ch_bit); in edma_stop()
591 edma_shadow0_write_array(ecc, SH_SECR, idx, ch_bit); in edma_stop()
592 edma_write_array(ecc, EDMA_EMCR, idx, ch_bit); in edma_stop()
595 edma_shadow0_write_array(ecc, SH_ICR, idx, ch_bit); in edma_stop()
597 dev_dbg(ecc->dev, "EER%d %08x\n", idx, in edma_stop()
598 edma_shadow0_read_array(ecc, SH_EER, idx)); in edma_stop()
613 edma_shadow0_write_array(echan->ecc, SH_EECR, in edma_pause()
623 edma_shadow0_write_array(echan->ecc, SH_EESR, in edma_resume()
630 struct edma_cc *ecc = echan->ecc; in edma_trigger_channel() local
635 edma_shadow0_write_array(ecc, SH_ESR, idx, ch_bit); in edma_trigger_channel()
637 dev_dbg(ecc->dev, "ESR%d %08x\n", idx, in edma_trigger_channel()
638 edma_shadow0_read_array(ecc, SH_ESR, idx)); in edma_trigger_channel()
643 struct edma_cc *ecc = echan->ecc; in edma_clean_channel() local
648 dev_dbg(ecc->dev, "EMR%d %08x\n", idx, in edma_clean_channel()
649 edma_read_array(ecc, EDMA_EMR, idx)); in edma_clean_channel()
650 edma_shadow0_write_array(ecc, SH_ECR, idx, ch_bit); in edma_clean_channel()
652 edma_write_array(ecc, EDMA_EMCR, idx, ch_bit); in edma_clean_channel()
654 edma_shadow0_write_array(ecc, SH_SECR, idx, ch_bit); in edma_clean_channel()
655 edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); in edma_clean_channel()
662 struct edma_cc *ecc = echan->ecc; in edma_assign_channel_eventq() local
668 eventq_no = ecc->default_queue; in edma_assign_channel_eventq()
669 if (eventq_no >= ecc->num_tc) in edma_assign_channel_eventq()
673 edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit), in edma_assign_channel_eventq()
680 struct edma_cc *ecc = echan->ecc; in edma_alloc_channel() local
683 if (!test_bit(echan->ch_num, ecc->channels_mask)) { in edma_alloc_channel()
684 dev_err(ecc->dev, "Channel%d is reserved, can not be used!\n", in edma_alloc_channel()
690 edma_or_array2(ecc, EDMA_DRAE, 0, EDMA_REG_ARRAY_INDEX(channel), in edma_alloc_channel()
729 struct edma_cc *ecc = echan->ecc; in edma_execute() local
754 edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param); in edma_execute()
779 edma_link(ecc, echan->slot[i], echan->slot[i + 1]); in edma_execute()
791 edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]); in edma_execute()
793 edma_link(ecc, echan->slot[nslots - 1], in edma_execute()
794 echan->ecc->dummy_slot); in edma_execute()
1068 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); in edma_prep_slave_sg()
1198 echan->slot[1] = edma_alloc_slot(echan->ecc, in edma_prep_dma_memcpy()
1390 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); in edma_prep_dma_cyclic()
1502 struct edma_cc *ecc = data; in dma_irq_handler() local
1508 ctlr = ecc->id; in dma_irq_handler()
1512 dev_vdbg(ecc->dev, "dma_irq_handler\n"); in dma_irq_handler()
1514 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0); in dma_irq_handler()
1516 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1); in dma_irq_handler()
1519 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1); in dma_irq_handler()
1522 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0); in dma_irq_handler()
1536 edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot)); in dma_irq_handler()
1537 edma_completion_handler(&ecc->slave_chans[channel]); in dma_irq_handler()
1541 edma_shadow0_write(ecc, SH_IEVAL, 1); in dma_irq_handler()
1547 struct edma_cc *ecc = echan->ecc; in edma_error_handler() local
1557 err = edma_read_slot(ecc, echan->slot[0], &p); in edma_error_handler()
1588 static inline bool edma_error_pending(struct edma_cc *ecc) in edma_error_pending() argument
1590 if (edma_read_array(ecc, EDMA_EMR, 0) || in edma_error_pending()
1591 edma_read_array(ecc, EDMA_EMR, 1) || in edma_error_pending()
1592 edma_read(ecc, EDMA_QEMR) || edma_read(ecc, EDMA_CCERR)) in edma_error_pending()
1601 struct edma_cc *ecc = data; in dma_ccerr_handler() local
1607 ctlr = ecc->id; in dma_ccerr_handler()
1611 dev_vdbg(ecc->dev, "dma_ccerr_handler\n"); in dma_ccerr_handler()
1613 if (!edma_error_pending(ecc)) { in dma_ccerr_handler()
1619 dev_err(ecc->dev, "%s: Error interrupt without error event!\n", in dma_ccerr_handler()
1621 edma_write(ecc, EDMA_EEVAL, 1); in dma_ccerr_handler()
1630 val = edma_read_array(ecc, EDMA_EMR, j); in dma_ccerr_handler()
1634 dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val); in dma_ccerr_handler()
1640 edma_write_array(ecc, EDMA_EMCR, j, BIT(i)); in dma_ccerr_handler()
1642 edma_shadow0_write_array(ecc, SH_SECR, j, in dma_ccerr_handler()
1644 edma_error_handler(&ecc->slave_chans[k]); in dma_ccerr_handler()
1648 val = edma_read(ecc, EDMA_QEMR); in dma_ccerr_handler()
1650 dev_dbg(ecc->dev, "QEMR 0x%02x\n", val); in dma_ccerr_handler()
1652 edma_write(ecc, EDMA_QEMCR, val); in dma_ccerr_handler()
1653 edma_shadow0_write(ecc, SH_QSECR, val); in dma_ccerr_handler()
1656 val = edma_read(ecc, EDMA_CCERR); in dma_ccerr_handler()
1658 dev_warn(ecc->dev, "CCERR 0x%08x\n", val); in dma_ccerr_handler()
1660 edma_write(ecc, EDMA_CCERRCLR, val); in dma_ccerr_handler()
1663 if (!edma_error_pending(ecc)) in dma_ccerr_handler()
1669 edma_write(ecc, EDMA_EEVAL, 1); in dma_ccerr_handler()
1677 struct edma_cc *ecc = echan->ecc; in edma_alloc_chan_resources() local
1678 struct device *dev = ecc->dev; in edma_alloc_chan_resources()
1684 } else if (ecc->tc_list) { in edma_alloc_chan_resources()
1686 echan->tc = &ecc->tc_list[ecc->info->default_queue]; in edma_alloc_chan_resources()
1694 echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num); in edma_alloc_chan_resources()
1721 struct device *dev = echan->ecc->dev; in edma_free_chan_resources()
1732 edma_free_slot(echan->ecc, echan->slot[i]); in edma_free_chan_resources()
1738 edma_set_chmap(echan, echan->ecc->dummy_slot); in edma_free_chan_resources()
1791 pos = edma_get_position(echan->ecc, echan->slot[0], dst); in edma_residue()
1807 while (edma_shadow0_read_array(echan->ecc, event_reg, idx) & ch_bit) { in edma_residue()
1808 pos = edma_get_position(echan->ecc, echan->slot[0], dst); in edma_residue()
1931 static void edma_dma_init(struct edma_cc *ecc, bool legacy_mode) in edma_dma_init() argument
1933 struct dma_device *s_ddev = &ecc->dma_slave; in edma_dma_init()
1935 s32 *memcpy_channels = ecc->info->memcpy_channels; in edma_dma_init()
1941 if (ecc->legacy_mode && !memcpy_channels) { in edma_dma_init()
1942 dev_warn(ecc->dev, in edma_dma_init()
1970 s_ddev->dev = ecc->dev; in edma_dma_init()
1974 m_ddev = devm_kzalloc(ecc->dev, sizeof(*m_ddev), GFP_KERNEL); in edma_dma_init()
1976 dev_warn(ecc->dev, "memcpy is disabled due to OoM\n"); in edma_dma_init()
1980 ecc->dma_memcpy = m_ddev; in edma_dma_init()
2003 m_ddev->dev = ecc->dev; in edma_dma_init()
2005 } else if (!ecc->legacy_mode) { in edma_dma_init()
2006 dev_info(ecc->dev, "memcpy is disabled\n"); in edma_dma_init()
2010 for (i = 0; i < ecc->num_channels; i++) { in edma_dma_init()
2011 struct edma_chan *echan = &ecc->slave_chans[i]; in edma_dma_init()
2012 echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i); in edma_dma_init()
2013 echan->ecc = ecc; in edma_dma_init()
2028 struct edma_cc *ecc) in edma_setup_from_hw() argument
2035 cccfg = edma_read(ecc, EDMA_CCCFG); in edma_setup_from_hw()
2038 ecc->num_region = BIT(value); in edma_setup_from_hw()
2041 ecc->num_channels = BIT(value + 1); in edma_setup_from_hw()
2044 ecc->num_qchannels = value * 2; in edma_setup_from_hw()
2047 ecc->num_slots = BIT(value + 4); in edma_setup_from_hw()
2050 ecc->num_tc = value + 1; in edma_setup_from_hw()
2052 ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false; in edma_setup_from_hw()
2055 dev_dbg(dev, "num_region: %u\n", ecc->num_region); in edma_setup_from_hw()
2056 dev_dbg(dev, "num_channels: %u\n", ecc->num_channels); in edma_setup_from_hw()
2057 dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels); in edma_setup_from_hw()
2058 dev_dbg(dev, "num_slots: %u\n", ecc->num_slots); in edma_setup_from_hw()
2059 dev_dbg(dev, "num_tc: %u\n", ecc->num_tc); in edma_setup_from_hw()
2060 dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no"); in edma_setup_from_hw()
2076 queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8), in edma_setup_from_hw()
2081 for (i = 0; i < ecc->num_tc; i++) { in edma_setup_from_hw()
2241 struct edma_cc *ecc = ofdma->of_dma_data; in of_edma_xlate() local
2246 if (!ecc || dma_spec->args_count < 1) in of_edma_xlate()
2249 for (i = 0; i < ecc->num_channels; i++) { in of_edma_xlate()
2250 echan = &ecc->slave_chans[i]; in of_edma_xlate()
2260 if (echan->ecc->legacy_mode && dma_spec->args_count == 1) in of_edma_xlate()
2263 if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 && in of_edma_xlate()
2264 dma_spec->args[1] < echan->ecc->num_tc) { in of_edma_xlate()
2265 echan->tc = &echan->ecc->tc_list[dma_spec->args[1]]; in of_edma_xlate()
2301 struct edma_cc *ecc; in edma_probe() local
2326 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); in edma_probe()
2327 if (!ecc) in edma_probe()
2330 ecc->dev = dev; in edma_probe()
2331 ecc->id = pdev->id; in edma_probe()
2332 ecc->legacy_mode = legacy_mode; in edma_probe()
2334 if (ecc->id < 0) in edma_probe()
2335 ecc->id = 0; in edma_probe()
2346 ecc->base = devm_ioremap_resource(dev, mem); in edma_probe()
2347 if (IS_ERR(ecc->base)) in edma_probe()
2348 return PTR_ERR(ecc->base); in edma_probe()
2350 platform_set_drvdata(pdev, ecc); in edma_probe()
2361 ret = edma_setup_from_hw(dev, info, ecc); in edma_probe()
2366 ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels, in edma_probe()
2367 sizeof(*ecc->slave_chans), GFP_KERNEL); in edma_probe()
2369 ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots), in edma_probe()
2372 ecc->channels_mask = devm_kcalloc(dev, in edma_probe()
2373 BITS_TO_LONGS(ecc->num_channels), in edma_probe()
2375 if (!ecc->slave_chans || !ecc->slot_inuse || !ecc->channels_mask) { in edma_probe()
2381 bitmap_fill(ecc->channels_mask, ecc->num_channels); in edma_probe()
2383 ecc->default_queue = info->default_queue; in edma_probe()
2390 bitmap_set(ecc->slot_inuse, reserved[i][0], in edma_probe()
2398 bitmap_clear(ecc->channels_mask, reserved[i][0], in edma_probe()
2403 for (i = 0; i < ecc->num_slots; i++) { in edma_probe()
2405 if (!test_bit(i, ecc->slot_inuse)) in edma_probe()
2406 edma_write_slot(ecc, i, &dummy_paramset); in edma_probe()
2417 ecc); in edma_probe()
2422 ecc->ccint = irq; in edma_probe()
2433 ecc); in edma_probe()
2438 ecc->ccerrint = irq; in edma_probe()
2441 ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY); in edma_probe()
2442 if (ecc->dummy_slot < 0) { in edma_probe()
2444 ret = ecc->dummy_slot; in edma_probe()
2450 if (!ecc->legacy_mode) { in edma_probe()
2455 ecc->tc_list = devm_kcalloc(dev, ecc->num_tc, in edma_probe()
2456 sizeof(*ecc->tc_list), GFP_KERNEL); in edma_probe()
2457 if (!ecc->tc_list) { in edma_probe()
2465 if (ret || i == ecc->num_tc) in edma_probe()
2468 ecc->tc_list[i].node = tc_args.np; in edma_probe()
2469 ecc->tc_list[i].id = i; in edma_probe()
2478 array_max = DIV_ROUND_UP(ecc->num_channels, BITS_PER_TYPE(u32)); in edma_probe()
2481 (u32 *)ecc->channels_mask, in edma_probe()
2492 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], in edma_probe()
2495 edma_write_array2(ecc, EDMA_DRAE, 0, 0, 0x0); in edma_probe()
2496 edma_write_array2(ecc, EDMA_DRAE, 0, 1, 0x0); in edma_probe()
2497 edma_write_array(ecc, EDMA_QRAE, 0, 0x0); in edma_probe()
2499 ecc->info = info; in edma_probe()
2502 edma_dma_init(ecc, legacy_mode); in edma_probe()
2504 for (i = 0; i < ecc->num_channels; i++) { in edma_probe()
2506 if (!test_bit(i, ecc->channels_mask)) in edma_probe()
2510 edma_assign_channel_eventq(&ecc->slave_chans[i], in edma_probe()
2513 edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot); in edma_probe()
2516 ecc->dma_slave.filter.map = info->slave_map; in edma_probe()
2517 ecc->dma_slave.filter.mapcnt = info->slavecnt; in edma_probe()
2518 ecc->dma_slave.filter.fn = edma_filter_fn; in edma_probe()
2520 ret = dma_async_device_register(&ecc->dma_slave); in edma_probe()
2526 if (ecc->dma_memcpy) { in edma_probe()
2527 ret = dma_async_device_register(ecc->dma_memcpy); in edma_probe()
2531 dma_async_device_unregister(&ecc->dma_slave); in edma_probe()
2537 of_dma_controller_register(node, of_edma_xlate, ecc); in edma_probe()
2544 edma_free_slot(ecc, ecc->dummy_slot); in edma_probe()
2565 struct edma_cc *ecc = dev_get_drvdata(dev); in edma_remove() local
2567 devm_free_irq(dev, ecc->ccint, ecc); in edma_remove()
2568 devm_free_irq(dev, ecc->ccerrint, ecc); in edma_remove()
2570 edma_cleanupp_vchan(&ecc->dma_slave); in edma_remove()
2574 dma_async_device_unregister(&ecc->dma_slave); in edma_remove()
2575 if (ecc->dma_memcpy) in edma_remove()
2576 dma_async_device_unregister(ecc->dma_memcpy); in edma_remove()
2577 edma_free_slot(ecc, ecc->dummy_slot); in edma_remove()
2587 struct edma_cc *ecc = dev_get_drvdata(dev); in edma_pm_suspend() local
2588 struct edma_chan *echan = ecc->slave_chans; in edma_pm_suspend()
2591 for (i = 0; i < ecc->num_channels; i++) { in edma_pm_suspend()
2601 struct edma_cc *ecc = dev_get_drvdata(dev); in edma_pm_resume() local
2602 struct edma_chan *echan = ecc->slave_chans; in edma_pm_resume()
2607 edma_write_slot(ecc, ecc->dummy_slot, &dummy_paramset); in edma_pm_resume()
2609 queue_priority_mapping = ecc->info->queue_priority_mapping; in edma_pm_resume()
2613 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], in edma_pm_resume()
2616 for (i = 0; i < ecc->num_channels; i++) { in edma_pm_resume()
2619 edma_or_array2(ecc, EDMA_DRAE, 0, in edma_pm_resume()