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/linux-6.1.9/arch/arm64/boot/dts/qcom/
Dsc7280-herobrine-villager-r1.dts32 "TX SWR_ADC0", "ADC1_OUTPUT",
33 "TX SWR_ADC1", "ADC2_OUTPUT",
34 "TX SWR_ADC2", "ADC3_OUTPUT",
35 "TX SWR_DMIC0", "DMIC1_OUTPUT",
36 "TX SWR_DMIC1", "DMIC2_OUTPUT",
37 "TX SWR_DMIC2", "DMIC3_OUTPUT",
38 "TX SWR_DMIC3", "DMIC4_OUTPUT",
39 "TX SWR_DMIC4", "DMIC5_OUTPUT",
40 "TX SWR_DMIC5", "DMIC6_OUTPUT",
41 "TX SWR_DMIC6", "DMIC7_OUTPUT",
[all …]
Dsc7280-crd-r3.dts100 "TX SWR_ADC0", "ADC1_OUTPUT",
101 "TX SWR_ADC1", "ADC2_OUTPUT",
102 "TX SWR_ADC2", "ADC3_OUTPUT",
103 "TX SWR_DMIC0", "DMIC1_OUTPUT",
104 "TX SWR_DMIC1", "DMIC2_OUTPUT",
105 "TX SWR_DMIC2", "DMIC3_OUTPUT",
106 "TX SWR_DMIC3", "DMIC4_OUTPUT",
107 "TX SWR_DMIC4", "DMIC5_OUTPUT",
108 "TX SWR_DMIC5", "DMIC6_OUTPUT",
109 "TX SWR_DMIC6", "DMIC7_OUTPUT",
[all …]
Dsc7280-herobrine-audio-wcd9385.dtsi23 "TX SWR_ADC0", "ADC1_OUTPUT",
24 "TX SWR_ADC1", "ADC2_OUTPUT",
25 "TX SWR_ADC2", "ADC3_OUTPUT",
26 "TX SWR_DMIC0", "DMIC1_OUTPUT",
27 "TX SWR_DMIC1", "DMIC2_OUTPUT",
28 "TX SWR_DMIC2", "DMIC3_OUTPUT",
29 "TX SWR_DMIC3", "DMIC4_OUTPUT",
30 "TX SWR_DMIC4", "DMIC5_OUTPUT",
31 "TX SWR_DMIC5", "DMIC6_OUTPUT",
32 "TX SWR_DMIC6", "DMIC7_OUTPUT",
[all …]
Dsc7280-idp.dtsi103 "TX SWR_ADC0", "ADC1_OUTPUT",
104 "TX SWR_ADC1", "ADC2_OUTPUT",
105 "TX SWR_ADC2", "ADC3_OUTPUT",
106 "TX SWR_DMIC0", "DMIC1_OUTPUT",
107 "TX SWR_DMIC1", "DMIC2_OUTPUT",
108 "TX SWR_DMIC2", "DMIC3_OUTPUT",
109 "TX SWR_DMIC3", "DMIC4_OUTPUT",
110 "TX SWR_DMIC4", "DMIC5_OUTPUT",
111 "TX SWR_DMIC5", "DMIC6_OUTPUT",
112 "TX SWR_DMIC6", "DMIC7_OUTPUT",
[all …]
/linux-6.1.9/drivers/spi/
Dspi-loopback-test.c85 .tx_buf = TX(0),
99 .tx_buf = TX(PAGE_SIZE - 4),
112 .tx_buf = TX(0),
137 .tx_buf = TX(0),
141 .tx_buf = TX(SPI_TEST_MAX_SIZE_HALF),
154 .tx_buf = TX(64),
158 .tx_buf = TX(0),
172 .tx_buf = TX(0),
175 .tx_buf = TX(64),
188 .tx_buf = TX(0),
[all …]
/linux-6.1.9/Documentation/devicetree/bindings/display/bridge/
Drenesas,dw-hdmi.yaml7 title: Renesas R-Car DWC HDMI TX Encoder
13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
23 - renesas,r8a774a1-hdmi # for RZ/G2M compatible HDMI TX
24 - renesas,r8a774b1-hdmi # for RZ/G2N compatible HDMI TX
25 - renesas,r8a774e1-hdmi # for RZ/G2H compatible HDMI TX
26 - renesas,r8a7795-hdmi # for R-Car H3 compatible HDMI TX
27 - renesas,r8a7796-hdmi # for R-Car M3-W compatible HDMI TX
28 - renesas,r8a77961-hdmi # for R-Car M3-W+ compatible HDMI TX
29 - renesas,r8a77965-hdmi # for R-Car M3-N compatible HDMI TX
Dsynopsys,dw-hdmi.yaml7 title: Common Properties for Synopsys DesignWare HDMI TX Controller
14 TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
16 bindings for the platform-specific integrations of the DWC HDMI TX.
/linux-6.1.9/Documentation/devicetree/bindings/net/
Dmicrel-ksz90x1.txt51 - txen-skew-ps : Skew control of TX CTL pad
56 - txd0-skew-ps : Skew control of TX data 0 pad
57 - txd1-skew-ps : Skew control of TX data 1 pad
58 - txd2-skew-ps : Skew control of TX data 2 pad
59 - txd3-skew-ps : Skew control of TX data 3 pad
138 - txc-skew-ps : Skew control of TX clock pad
143 - txen-skew-ps : Skew control of TX CTL pad
148 - txd0-skew-ps : Skew control of TX data 0 pad
149 - txd1-skew-ps : Skew control of TX data 1 pad
150 - txd2-skew-ps : Skew control of TX data 2 pad
[all …]
Dxilinx_axienet.txt7 segments of memory for buffering TX and RX, as well as the capability of
8 offloading TX/RX checksum calculation off the processor.
24 - interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
26 specified, the TX/RX DMA interrupts should be on that node
38 - xlnx,txcsum : 0 or empty for disabling TX checksum offload,
39 1 to enable partial TX checksum offload,
40 2 to enable full TX checksum offload
66 device (DMA registers and DMA TX/RX interrupts) rather
Dethernet-controller.yaml77 # RX and TX delays are added by the MAC when required
80 # RGMII with internal RX and TX delays provided by the PHY,
81 # the MAC should not add the RX or TX delays in this case
88 # RGMII with internal TX delay provided by the PHY, the MAC
89 # should not add an TX delay in this case
239 controllers that have configurable TX internal delays. If this
240 property is present then the MAC applies the TX delay.
/linux-6.1.9/Documentation/devicetree/bindings/sound/
Dgoogle,sc7280-herobrine.yaml111 "TX SWR_ADC0", "ADC1_OUTPUT",
112 "TX SWR_ADC1", "ADC2_OUTPUT",
113 "TX SWR_ADC2", "ADC3_OUTPUT",
114 "TX SWR_DMIC0", "DMIC1_OUTPUT",
115 "TX SWR_DMIC1", "DMIC2_OUTPUT",
116 "TX SWR_DMIC2", "DMIC3_OUTPUT",
117 "TX SWR_DMIC3", "DMIC4_OUTPUT";
Dnvidia,tegra30-ahub.txt61 For TX CIFs, the numbers indicate the bit position within the AHUB routing
62 registers (APBIF 0..3 TX, I2S 0..5 TX, DAM 0..2 TX, SPDIF TX 0..1).
Drockchip,i2s-tdm.yaml47 - description: clock for TX
92 description: Use TX BCLK/LRCK for both TX and RX.
96 description: Use RX BCLK/LRCK for both TX and RX.
114 Defines the mapping of I2S TX sdos to I2S data bus lines.
/linux-6.1.9/sound/soc/fsl/
Dimx-audio-rpmsg.c39 spin_lock_irqsave(&info->lock[TX], flags); in imx_audio_rpmsg_cb()
43 msg->r_msg.param.buffer_tail %= info->num_period[TX]; in imx_audio_rpmsg_cb()
44 spin_unlock_irqrestore(&info->lock[TX], flags); in imx_audio_rpmsg_cb()
45 info->callback[TX](info->callback_param[TX]); in imx_audio_rpmsg_cb()
Dfsl_ssi.c57 #define TX 1 macro
407 int dir = tx ? TX : RX; in fsl_ssi_config_enable()
427 srcr = vals[RX].srcr | vals[TX].srcr; in fsl_ssi_config_enable()
428 stcr = vals[RX].stcr | vals[TX].stcr; in fsl_ssi_config_enable()
429 sier = vals[RX].sier | vals[TX].sier; in fsl_ssi_config_enable()
511 int adir = tx ? RX : TX; in fsl_ssi_config_disable()
512 int dir = tx ? TX : RX; in fsl_ssi_config_disable()
593 vals[TX].sier = SSI_SIER_TFE0_EN | FSLSSI_SIER_DBG_TX_FLAGS; in fsl_ssi_setup_regvals()
594 vals[TX].stcr = SSI_STCR_TFEN0; in fsl_ssi_setup_regvals()
595 vals[TX].scr = SSI_SCR_SSIEN | SSI_SCR_TE; in fsl_ssi_setup_regvals()
[all …]
/linux-6.1.9/Documentation/input/devices/
Dwalkera0701.rst24 Cable: (walkera TX to parport)
26 Walkera WK-0701 TX S-VIDEO connector::
28 (back side of TX)
45 walkera0701 module, check dmesg for error messages. Connect TX to PC by
46 cable and run jstest /dev/input/js0 to see values from TX. If no value can
47 be changed by TX "joystick", check output from /proc/interrupts. Value for
48 (usually irq7) parport must increase if TX is on.
113 directly controlled from TX). Binary representations are the same as in first
/linux-6.1.9/Documentation/networking/
Dmac80211-auth-assoc-deauth.txt31 mac80211->driver: TX directed probe request
35 mac80211->driver: TX auth frame
39 mac80211->driver: TX auth frame
59 mac80211->driver: TX assoc
86 mac80211->driver: TX deauth/disassoc
Ddriver.rst45 And then at the end of your TX reclamation event handling::
73 For example, this means that it is not allowed for your TX
74 mitigation scheme to let TX packets "hang out" in the TX
75 ring unreclaimed forever if no new TX packets are sent.
Daf_xdp.rst25 TX ring. A socket can receive packets on the RX ring and it can send
26 packets on the TX ring. These rings are registered and sized with the
28 to have at least one of these rings for each socket. An RX or TX
30 UMEM. RX and TX can share the same UMEM so that a packet does not have
31 to be copied between RX and TX. Moreover, if a packet needs to be kept
48 space, for either TX or RX. Thus, the frame addrs appearing in the
50 TX ring. In summary, the RX and FILL rings are used for the RX path
51 and the TX and COMPLETION rings are used for the TX path.
65 process has to create its own socket with associated RX and TX rings,
129 TX. All rings are single-producer/single-consumer, so the user-space
[all …]
/linux-6.1.9/Documentation/devicetree/bindings/dma/
Dstericsson,dma40.yaml71 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
72 50: Hash Accelerator 1 TX
73 51: memcpy TX (to be used by the DMA driver for memcpy operations)
84 62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
85 63: Hash Accelerator 0 TX
/linux-6.1.9/drivers/net/dsa/sja1105/
DKconfig21 - SJA1110A (Gen. 3, SGMII, TT-Ethernet, 100base-TX PHY, 10 ports)
22 - SJA1110B (Gen. 3, SGMII, TT-Ethernet, 100base-TX PHY, 9 ports)
23 - SJA1110C (Gen. 3, SGMII, TT-Ethernet, 100base-TX PHY, 7 ports)
24 - SJA1110D (Gen. 3, SGMII, TT-Ethernet, no 100base-TX PHY, 7 ports)
/linux-6.1.9/drivers/usb/chipidea/
Dudc.c63 return num + ((dir == TX) ? 16 : 0); in hw_ep_bit()
129 (dir == TX) ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0); in hw_ep_disable()
146 if (dir == TX) { in hw_ep_enable()
179 u32 mask = (dir == TX) ? ENDPTCTRL_TXS : ENDPTCTRL_RXS; in hw_ep_get_halt()
231 u32 mask_xs = (dir == TX) ? ENDPTCTRL_TXS : ENDPTCTRL_RXS; in hw_ep_set_halt()
232 u32 mask_xr = (dir == TX) ? ENDPTCTRL_TXR : ENDPTCTRL_RXR; in hw_ep_set_halt()
377 if (hwep->type == USB_ENDPOINT_XFER_ISOC && hwep->dir == TX) { in add_td_to_list()
423 return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num; in _usb_addr()
457 if (hwreq->req.zero && hwreq->req.length && hwep->dir == TX in prepare_td_for_non_sg()
715 if (hwep->dir == TX) { in _hardware_dequeue()
[all …]
/linux-6.1.9/Documentation/devicetree/bindings/media/i2c/
Dtc358743.txt1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
/linux-6.1.9/arch/arm64/boot/dts/amlogic/
Dmeson-gxbb-nanopi-k2.dts237 gpio-line-names = "UART TX", "UART RX", "Power Control", "Power Key In",
250 "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
251 "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3",
286 "Bluetooth UART TX", "Bluetooth UART RX",
/linux-6.1.9/Documentation/networking/device_drivers/ethernet/google/
Dgve.rst33 - Bar2 - IRQ, RX and TX doorbells
138 - Every TX and RX queue is assigned a notification block.
140 - TX and RX buffers queues, which send descriptors to the device, use MMIO
143 - RX and TX completion queues, which receive descriptors from the device, use a
150 - It's the driver's responsibility to ensure that the RX and TX completion
154 - TX packets have a 16 bit completion_tag and RX buffers have a 16 bit
155 buffer_id. These will be returned on the TX completion and RX queues

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