Searched refs:DMA (Results 1 – 25 of 671) sorted by relevance
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| /linux-6.1.9/Documentation/driver-api/media/drivers/ |
| D | pxa_camera.rst | 13 This is due to DMA constraints, which transfers only planes of 8 byte
26 capture. The new buffers are "appended" at the tail of the DMA chain, and
46 | | DMA: stop | | DMA: stop | |
53 | | DMA hotlink missed | | Capture running | |
56 | | DMA: stop | / | DMA: run | | |
58 | ^ /DMA still | | channels |
59 | | capture list / running | DMA Irq End | not |
66 | DMA: run | | DMA: run | |
75 | DMA: run | | DMA: stop |
84 - "DMA: stop" means all 3 DMA channels are stopped
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| /linux-6.1.9/Documentation/translations/zh_CN/PCI/ |
| D | pci.rst | 55 - 设置DMA掩码大小（对于流式和一致的DMA）
60 - 启用DMA/处理引擎
66 - 停止所有DMA活动
67 - 释放DMA缓冲区（包括一致性和数据流式）
183 - 设置DMA掩码大小（对于流式和一致的DMA）
188 - 启用DMA/处理引擎
216 pci_set_master()将通过设置PCI_COMMAND寄存器中的总线主控位来启用DMA。
217 ``pci_clear_master()`` 将通过清除总线主控位来禁用DMA，它还修复了延迟计时器的
250 设置DMA掩码大小
253 如果下面有什么不明白的地方，请参考使用通用设备的动态DMA映射。本节只是提醒大家，
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| /linux-6.1.9/drivers/dma/ |
| D | Kconfig | 3 # DMA engine configuration
7 bool "DMA Engine support"
10 DMA engines can do asynchronous data transfers without
14 DMA Device drivers supported by the configured arch, it may
18 bool "DMA Engine debugging"
22 say N here. This enables DMA engine core and driver debugging.
25 bool "DMA Engine verbose debugging"
30 the DMA engine core and drivers.
35 comment "DMA Devices"
74 provide DMA engine support. This includes the original ARM
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| /linux-6.1.9/Documentation/devicetree/bindings/dma/ |
| D | fsl-imx-dma.txt | 1 * Freescale Direct Memory Access (DMA) Controller for i.MX
3 This document will only describe differences to the generic DMA Controller and
4 DMA request bindings as described in dma/dma.txt .
6 * DMA controller
10 - reg : Should contain DMA registers location and length
11 - interrupts : First item should be DMA interrupt, second one is optional and
12 should contain DMA Error interrupt
16 - dma-channels : Number of DMA channels supported. Should be 16.
18 - dma-requests : Number of DMA requests supported.
32 * DMA client
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| D | ti-dma-crossbar.txt | 1 Texas Instruments DMA Crossbar (DMA request router)
4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
7 - #dma-cells: Should be set to match with the DMA controller's dma-cells
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
12 The DMA controller node need to have the following poroperties:
13 - dma-requests: Number of DMA requests the controller can handle
17 - ti,reserved-dma-request-ranges: DMA request ranges which should not be used
18 when mapping xbar input to DMA request, they are either
23 When requesting channel via ti,dra7-dma-crossbar, the DMA clinet must request
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| D | st,stm32-dma.yaml | 7 title: STMicroelectronics STM32 DMA Controller bindings
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
14 channel: a phandle to the DMA controller plus the following four integer cells:
17 3. A 32bit mask specifying the DMA channel configuration which are device
33 4. A 32bit bitfield value specifying DMA features which are device dependent:
34 -bit 0-1: DMA FIFO threshold selection
39 -bit 2: DMA direct mode
41 0x1: Direct mode: each DMA request immediately initiates a transfer
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| D | mpc512x-dma.txt | 1 * Freescale MPC512x and MPC8308 DMA Controller
3 The DMA controller in Freescale MPC512x and MPC8308 SoCs can move
7 Refer to "Generic DMA Controller and DMA request bindings" in
12 - reg: should contain the DMA controller registers location and length;
13 - interrupt for the DMA controller: syntax of interrupt client node
15 - #dma-cells: the length of the DMA specifier, must be <1>.
16 Each channel of this DMA controller has a peripheral request line,
29 DMA clients must use the format described in dma/dma.txt file.
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| D | sprd-dma.txt | 1 * Spreadtrum DMA controller
3 This binding follows the generic DMA bindings defined in dma.txt.
7 - reg: Should contain DMA registers location and length.
11 - dma-channels : Number of DMA channels supported. Should be 32.
12 - clock-names: Should contain the clock of the DMA controller.
16 - #dma-channels : Number of DMA channels supported. Should be 32.
33 DMA clients connected to the Spreadtrum DMA controller must use the format
36 1. A phandle pointing to the DMA controller.
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| D | mmp-dma.txt | 1 * MARVELL MMP DMA controller
3 Marvell Peripheral DMA Controller
8 - reg: Should contain DMA registers location and length.
9 - interrupts: Either contain all of the per-channel DMA interrupts
13 - dma-channels: Number of DMA channels supported by the controller (defaults
16 - dma-requests: Number of DMA requestor lines supported by the controller
28 * while DMA controller may not able to distinguish the irq channel
43 * Dmaengine driver (DMA controller) distinguish irq channel via
54 Marvell Two Channel DMA Controller used specifically for audio
59 - reg: Should contain DMA registers location and length.
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| D | intel,ldma.yaml | 7 title: Lightning Mountain centralized DMA controllers.
34 The first cell is the peripheral's DMA request line.
61 DMA descriptor polling counter is used to control the poling mechanism
67 DMA byte enable is only valid for DMA write(RX).
68 Byte enable(1) means DMA write will be based on the number of dwords
74 DMA descriptor read back to make sure data and desc synchronization.
79 Enable RX dynamic burst write. When it is enabled, the DMA does RX dynamic burst;
80 if it is disabled, the DMA RX will still support programmable fixed burst size of 2,4,8,16.
81 It only applies to RX DMA and memcopy DMA.
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| D | dma-common.yaml | 7 title: DMA Engine Generic Binding
13 Generic binding to provide a way for a driver using DMA Engine to
14 retrieve the DMA request or channel information that goes from a
15 hardware device to a DMA controller.
25 Used to provide DMA controller specific information.
29 Bitmask of available DMA channels in ascending order that are
43 Number of DMA channels supported by the controller.
48 Number of DMA request signals supported by the controller.
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| D | dma-router.yaml | 7 title: DMA Router Generic Binding
16 DMA routers are transparent IP blocks used to route DMA request
17 lines from devices to the DMA controller. Some SoCs (like TI DRA7x)
18 have more peripherals integrated with DMA requests than what the DMA
30 Array of phandles to the DMA controllers the router can direct
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| /linux-6.1.9/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | dma.txt | 1 * Freescale DMA Controllers
3 ** Freescale Elo DMA Controller
4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
10 - reg : DMA General Status Register, i.e. DGSR which contains
11 status for all the 4 DMA channels
13 DMA channels and the address space of the DMA controller
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
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| /linux-6.1.9/Documentation/devicetree/bindings/soc/ti/ |
| D | keystone-navigator-dma.txt | 1 Keystone Navigator DMA Controller
4 on keystone devices. The Keystone Navigator DMA driver sets up the dma
9 an internal packet DMA module which is used as an infrastructure DMA
12 Navigator DMA cloud layout:
17 |-> DMA instance #0
19 |-> DMA instance #1
23 |-> DMA instance #n
25 Navigator DMA properties:
34 into DMA and the DMA uses it as the physical addresses to reach queue
36 they are relevant only from DMA perspective. The QMSS may not choose to
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| /linux-6.1.9/Documentation/core-api/ |
| D | dma-isa-lpc.rst | 2 DMA with ISA and LPC devices
7 This document describes how to do DMA transfers using the old ISA DMA
9 uses the same DMA system so it will be around for quite some time.
14 To do ISA style DMA you need to include two headers::
19 The first is the generic DMA API used to convert virtual addresses to
22 The second contains the routines specific to ISA DMA transfers. Since
30 The ISA DMA controller has some very strict requirements on which
34 (You usually need a special buffer for DMA transfers instead of
37 The DMA-able address space is the lowest 16 MB of _physical_ memory.
44 Unfortunately the memory available for ISA DMA is scarce so unless you
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| D | dma-api-howto.rst | 2 Dynamic DMA mapping Guide
9 This is a guide to device driver writers on how to use the DMA API
11 DMA-API.txt.
13 CPU and DMA addresses
16 There are several kinds of addresses involved in the DMA API, and it's
31 registers at an MMIO address, or if it performs DMA to read or write system
37 From a device's point of view, DMA uses the bus address space, but it may
40 so devices only need to use 32-bit DMA addresses.
75 If the device supports DMA, the driver sets up a buffer using kmalloc() or
79 cannot because DMA doesn't go through the CPU virtual memory system.
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| /linux-6.1.9/Documentation/arm/stm32/ |
| D | stm32-dma-mdma-chaining.rst | 4 STM32 DMA-MDMA chaining
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
15 direct memory access controllers (DMA).
17 STM32MP1 SoCs embed both STM32 DMA and STM32 MDMA controllers. STM32 DMA
18 request routing capabilities are enhanced by a DMA request multiplexer
23 STM32 DMAMUX routes any DMA request from a given peripheral to any STM32 DMA
24 controller (STM32MP1 counts two STM32 DMA controllers) channels.
26 **STM32 DMA**
28 STM32 DMA is mainly used to implement central data buffer storage (usually in
35 STM32 MDMA (Master DMA) is mainly used to manage direct data transfers between
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| /linux-6.1.9/drivers/dma/sh/ |
| D | Kconfig | 3 # DMA engine configuration for sh
11 # DMA Engine Helpers
15 bool "Renesas SuperH DMA Engine support"
22 Enable support for the Renesas SuperH DMA controllers.
25 # DMA Controllers
32 Enable support for the Renesas SuperH DMA controllers.
35 tristate "Renesas R-Car Gen{2,3} and RZ/G{1,2} DMA Controller"
39 This driver supports the general purpose DMA controller found in the
43 tristate "Renesas USB-DMA Controller"
48 This driver supports the USB-DMA controller found in the Renesas
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| /linux-6.1.9/Documentation/driver-api/dmaengine/ |
| D | client.rst | 2 DMA Engine API Guide
7 .. note:: For DMA Engine usage in async_tx please see:
11 Below is a guide to device driver writers on how to use the Slave-DMA API of the
12 DMA Engine. This is applicable only for slave DMA usage only.
14 DMA usage
17 The slave DMA usage consists of following steps:
19 - Allocate a DMA slave channel
31 1. Allocate a DMA slave channel
33 Channel allocation is slightly different in the slave DMA context,
34 client drivers typically need a channel from a particular DMA
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| /linux-6.1.9/Documentation/i2c/ |
| D | dma-considerations.rst | 2 Linux I2C and DMA
6 transferred are small, it is not considered a prime user of DMA access. At this
7 time of writing, only 10% of I2C bus master drivers have DMA support
9 DMA for it will likely add more overhead than a plain PIO transfer.
11 Therefore, it is *not* mandatory that the buffer of an I2C message is DMA safe.
13 rarely used. However, it is recommended to use a DMA-safe buffer if your
14 message size is likely applicable for DMA. Most drivers have this threshold
18 I2C bus master driver is using USB as a bridge, then you need to have DMA
24 For clients, if you use a DMA safe buffer in i2c_msg, set the I2C_M_DMA_SAFE
25 flag with it. Then, the I2C core and drivers know they can safely operate DMA
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| /linux-6.1.9/drivers/dma/ti/ |
| D | Kconfig | 3 # Texas Instruments DMA drivers
7 tristate "Texas Instruments CPPI 4.1 DMA support"
11 The Communications Port Programming Interface (CPPI) 4.1 DMA engine
22 Enable support for the TI EDMA (Enhanced DMA) controller. This DMA
34 Enable support for the TI sDMA (System DMA or DMA4) controller. This
35 DMA engine is found on OMAP and DRA7xx parts.
47 Enable support for the TI UDMA (Unified DMA) controller. This
48 DMA engine is used in AM65x and j721e.
55 Say y here to support the K3 NAVSS DMA glue interface
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| /linux-6.1.9/Documentation/driver-api/ |
| D | dma-buf.rst | 5 hardware (DMA) access across multiple device drivers and subsystems, and
17 Shared DMA Buffers
23 Any device driver which wishes to be a part of DMA buffer sharing, can do so as
55 Mostly a DMA buffer file descriptor is simply an opaque object for userspace,
85 - Memory mapping the contents of the DMA buffer is also supported. See the
86 discussion below on `CPU Access to DMA Buffer Objects`_ for the full details.
88 - The DMA buffer FD is also pollable, see `Implicit Fence Poll Support`_ below for
91 - The DMA buffer FD also supports a few dma-buf-specific ioctls, see
92 `DMA Buffer ioctls`_ below for details.
94 Basic Operation and Device DMA Access
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| /linux-6.1.9/Documentation/driver-api/usb/ |
| D | dma.rst | 1 USB DMA
5 over how DMA may be used to perform I/O operations. The APIs are detailed
11 The big picture is that USB drivers can continue to ignore most DMA issues,
12 though they still must provide DMA-ready buffers (see
14 the 2.4 (and earlier) kernels, or they can now be DMA-aware.
16 DMA-aware usb drivers:
18 - New calls enable DMA-aware drivers, letting them allocate dma buffers and
25 - "usbcore" will map this DMA address, if a DMA-aware driver didn't do
29 - There's a new "generic DMA API", parts of which are usable by USB device
41 IOMMU to manage the DMA mappings. It can cost MUCH more to set up and
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| /linux-6.1.9/drivers/dma/qcom/ |
| D | Kconfig | 8 Enable support for the Qualcomm Application Data Mover (ADM) DMA
10 This controller provides DMA capabilities for both general purpose
14 tristate "QCOM BAM DMA support"
19 Enable support for the QCOM BAM DMA controller. This controller
20 provides DMA capabilities for a variety of on-chip devices.
23 tristate "Qualcomm Technologies GPI DMA support"
28 Enable support for the QCOM GPI DMA controller. This controller
29 provides DMA capabilities for a variety of peripheral buses such
40 Each DMA device requires one management interface driver
54 purpose slave DMA.
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| /linux-6.1.9/Documentation/devicetree/bindings/powerpc/4xx/ |
| D | ppc440spe-adma.txt | 1 PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator)
4 are specified hereby. These are I2O/DMA, DMA and XOR nodes
5 for DMA engines and Memory Queue Module node. The latter is used
9 DMA devices.
28 ii) The DMA node
33 - cell-index : 1 cell, hardware index of the DMA engine
39 and DMA Error IRQ (on UIC1). The latter is common
40 for both DMA engines>.
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