Lines Matching refs:DMA
13 This is due to DMA constraints, which transfers only planes of 8 byte
26 capture. The new buffers are "appended" at the tail of the DMA chain, and
46 | | DMA: stop | | DMA: stop | |
53 | | DMA hotlink missed | | Capture running | |
56 | | DMA: stop | / | DMA: run | | |
58 | ^ /DMA still | | channels |
59 | | capture list / running | DMA Irq End | not |
66 | DMA: run | | DMA: run | |
75 | DMA: run | | DMA: stop |
84 - "DMA: stop" means all 3 DMA channels are stopped
85 - "DMA: run" means at least 1 DMA channel is still running
87 DMA usage
90 a) DMA flow
94 starts the DMA chain.
96 The DMA chain starts transferring data into videobuffer RAM pages.
97 When all pages are transferred, the DMA irq is raised on "ENDINTR" status
99 The DMA irq handler marks the videobuffer as "done", and removes it from
101 Meanwhile, the next videobuffer (if there is one), is transferred by DMA
103 On the DMA irq of the last videobuffer, the QCI is stopped.
105 b) DMA prepared buffer will have this structure
146 c) DMA hot chaining timeslice issue
148 As DMA chaining is done while DMA _is_ running, the linking may be done
149 while the DMA jumps from one Videobuffer to another. On the schema, that
152 - DMA chain is Videobuffer1 + Videobuffer2
154 - DMA controller finishes Videobuffer2, and DMA stops
164 +----+ +-- DMA DDADR loads DDADR_STOP
169 - the DMA irq handler is called, which terminates Videobuffer2
170 - Videobuffer3 capture is not scheduled on DMA chain (as it stopped !!!)
181 DMA DDADR still is DDADR_STOP
184 This checks if the DMA is finished and a buffer is still on the
186 and Videobuffer3 is scheduled on DMA chain.
187 - the DMA irq handler finishes
191 If DMA stops just after pxa_camera_check_link_miss() reads DDADR()
192 value, we have the guarantee that the DMA irq handler will be called back
193 when the DMA will finish the buffer, and pxa_camera_check_link_miss() will