| /linux-3.4.99/drivers/gpu/drm/gma500/ |
| D | oaktrail_crtc.c | 308 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in oaktrail_crtc_mode_set() local
427 dpll = 0; /*BIT16 = 0 for 100MHz reference */ in oaktrail_crtc_mode_set()
441 dpll |= DPLL_VGA_MODE_DIS; in oaktrail_crtc_mode_set()
444 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set()
447 dpll |= DPLLA_MODE_LVDS; in oaktrail_crtc_mode_set()
449 dpll |= DPLLB_MODE_DAC_SERIAL; in oaktrail_crtc_mode_set()
455 dpll |= DPLL_DVO_HIGH_SPEED; in oaktrail_crtc_mode_set()
456 dpll |= in oaktrail_crtc_mode_set()
463 dpll |= (1 << (clock.p1 - 2)) << 17; in oaktrail_crtc_mode_set()
465 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set()
[all …]
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| D | mdfld_intel_display.c | 787 u32 dpll = 0, fp = 0; in mdfld_crtc_mode_set() local
1073 dpll = REG_READ(dpll_reg); in mdfld_crtc_mode_set()
1075 if (dpll & DPLL_VCO_ENABLE) { in mdfld_crtc_mode_set()
1076 dpll &= ~DPLL_VCO_ENABLE; in mdfld_crtc_mode_set()
1077 REG_WRITE(dpll_reg, dpll); in mdfld_crtc_mode_set()
1086 dpll &= ~MDFLD_P1_MASK; in mdfld_crtc_mode_set()
1087 REG_WRITE(dpll_reg, dpll); in mdfld_crtc_mode_set()
1094 if (dpll & MDFLD_PWR_GATE_EN) { in mdfld_crtc_mode_set()
1095 dpll &= ~MDFLD_PWR_GATE_EN; in mdfld_crtc_mode_set()
1096 REG_WRITE(dpll_reg, dpll); in mdfld_crtc_mode_set()
[all …]
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| D | psb_intel_display.c | 610 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
654 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
656 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
657 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
659 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
663 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
664 dpll |= in psb_intel_crtc_mode_set()
669 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
672 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
675 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
[all …]
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| D | cdv_intel_display.c | 729 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
776 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
780 dpll |= 3; in cdv_intel_crtc_mode_set()
782 dpll |= PLL_REF_INPUT_DREFCLK; in cdv_intel_crtc_mode_set()
784 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
785 dpll |= DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
787 dpll |= DPLLB_MODE_LVDS; in cdv_intel_crtc_mode_set()
789 dpll |= DPLLB_MODE_DAC_SERIAL; in cdv_intel_crtc_mode_set()
806 REG_WRITE(dpll_reg, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
842 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set()
[all …]
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| D | mdfld_device.c | 361 u32 dpll = 0; in mdfld_restore_display_registers() local
513 dpll = PSB_RVDC32(dpll_reg); in mdfld_restore_display_registers()
515 if (!(dpll & DPLL_VCO_ENABLE)) { in mdfld_restore_display_registers()
519 if (dpll & MDFLD_PWR_GATE_EN) { in mdfld_restore_display_registers()
520 dpll &= ~MDFLD_PWR_GATE_EN; in mdfld_restore_display_registers()
521 PSB_WVDC32(dpll, dpll_reg); in mdfld_restore_display_registers()
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| /linux-3.4.99/arch/arm/mach-omap1/ |
| D | sram.S | 39 strh r0, [r2] @ set dpll into bypass mode
44 strh r0, [r2] @ write new dpll value
52 lock: ldrh r4, [r2], #0 @ read back dpll value
55 tst r4, #1 << 0 @ dpll rate locked?
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| /linux-3.4.99/drivers/ata/ |
| D | pata_hpt3x2n.c | 317 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
324 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
333 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
335 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
337 flags |= dpll; in hpt3x2n_qc_issue()
340 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
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| D | pata_hpt37x.c | 983 int dpll, adjust; in hpt37x_init_one() local
986 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; in hpt37x_init_one()
988 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; in hpt37x_init_one()
1016 if (dpll == 3) in hpt37x_init_one()
1022 MHz[clock_slot], MHz[dpll]); in hpt37x_init_one()
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| /linux-3.4.99/drivers/video/intelfb/ |
| D | intelfbhw.c | 682 static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, in intelfbhw_get_p1p2() argument
688 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2()
691 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff; in intelfbhw_get_p1p2()
695 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_get_p1p2()
697 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2()
700 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK; in intelfbhw_get_p1p2()
701 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_get_p1p2()
1048 u32 *dpll, *fp0, *fp1; in intelfbhw_mode_to_hw() local
1063 dpll = &hw->dpll_b; in intelfbhw_mode_to_hw()
1075 dpll = &hw->dpll_a; in intelfbhw_mode_to_hw()
[all …]
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| /linux-3.4.99/drivers/gpu/drm/i915/ |
| D | intel_display.c | 5161 u32 dpll, dspcntr, pipeconf, vsyncshift; in i9xx_crtc_mode_set() local
5240 dpll = DPLL_VGA_MODE_DIS; in i9xx_crtc_mode_set()
5244 dpll |= DPLLB_MODE_LVDS; in i9xx_crtc_mode_set()
5246 dpll |= DPLLB_MODE_DAC_SERIAL; in i9xx_crtc_mode_set()
5251 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; in i9xx_crtc_mode_set()
5253 dpll |= DPLL_DVO_HIGH_SPEED; in i9xx_crtc_mode_set()
5256 dpll |= DPLL_DVO_HIGH_SPEED; in i9xx_crtc_mode_set()
5260 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_crtc_mode_set()
5262 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_crtc_mode_set()
5264 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_crtc_mode_set()
[all …]
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| /linux-3.4.99/arch/arm/mach-s5p64x0/ |
| D | clock-s5p6450.c | 609 unsigned long dpll; in s5p6450_setup_clocks() local
629 dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON), in s5p6450_setup_clocks()
635 clk_fout_dpll.rate = dpll; in s5p6450_setup_clocks()
640 print_mhz(dpll)); in s5p6450_setup_clocks()
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| /linux-3.4.99/arch/arm/mach-omap2/ |
| D | sram242x.S | 269 str r0, [r4] @ set dpll ctrl val
282 beq pend @ jump over dpll relock
287 orr r8, r7, #0x3 @ val for lock dpll
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| D | sram243x.S | 269 str r0, [r4] @ set dpll ctrl val
282 beq pend @ jump over dpll relock
287 orr r8, r7, #0x3 @ val for lock dpll
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| D | sram34xx.S | 220 ldr r10, core_m2_mask_val @ modify m2 for core dpll
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| /linux-3.4.99/drivers/ide/ |
| D | hpt366.c | 853 u32 dpll = (f_high << 16) | f_low | 0x100; in hpt37x_calibrate_dpll() local
857 pci_write_config_dword(dev, 0x5c, dpll); in hpt37x_calibrate_dpll()
874 pci_read_config_dword (dev, 0x5c, &dpll); in hpt37x_calibrate_dpll()
875 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100)); in hpt37x_calibrate_dpll()
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| /linux-3.4.99/Documentation/networking/ |
| D | z8530drv.txt | 212 cards. Use "mode dpll" for clock source (see below).
251 clock dpll # clock source:
252 # dpll = normal half duplex operation
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