610 	u32 dpll = 0, fp = 0, dspcntr, pipeconf;  in psb_intel_crtc_mode_set()  local
654 	dpll = DPLL_VGA_MODE_DIS;  in psb_intel_crtc_mode_set()
656 		dpll |= DPLLB_MODE_LVDS;  in psb_intel_crtc_mode_set()
657 		dpll |= DPLL_DVO_HIGH_SPEED;  in psb_intel_crtc_mode_set()
659 		dpll |= DPLLB_MODE_DAC_SERIAL;  in psb_intel_crtc_mode_set()
663 		dpll |= DPLL_DVO_HIGH_SPEED;  in psb_intel_crtc_mode_set()
664 		dpll |=  in psb_intel_crtc_mode_set()
669 	dpll |= (1 << (clock.p1 - 1)) << 16;  in psb_intel_crtc_mode_set()
672 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;  in psb_intel_crtc_mode_set()
675 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;  in psb_intel_crtc_mode_set()
678 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;  in psb_intel_crtc_mode_set()
681 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;  in psb_intel_crtc_mode_set()
688 		dpll |= 3;  in psb_intel_crtc_mode_set()
690 	dpll |= PLL_REF_INPUT_DREFCLK;  in psb_intel_crtc_mode_set()
705 	dpll |= DPLL_VCO_ENABLE;  in psb_intel_crtc_mode_set()
714 	if (dpll & DPLL_VCO_ENABLE) {  in psb_intel_crtc_mode_set()
716 		REG_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);  in psb_intel_crtc_mode_set()
751 	REG_WRITE(dpll_reg, dpll);  in psb_intel_crtc_mode_set()
757 	REG_WRITE(dpll_reg, dpll);  in psb_intel_crtc_mode_set()
1119 	u32 dpll;  in psb_intel_crtc_clock_get()  local
1126 		dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B);  in psb_intel_crtc_clock_get()
1127 		if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)  in psb_intel_crtc_clock_get()
1134 		dpll = (pipe == 0) ?  in psb_intel_crtc_clock_get()
1138 		if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)  in psb_intel_crtc_clock_get()
1157 		    ffs((dpll &  in psb_intel_crtc_clock_get()
1162 		if ((dpll & PLL_REF_INPUT_MASK) ==  in psb_intel_crtc_clock_get()
1169 		if (dpll & PLL_P1_DIVIDE_BY_TWO)  in psb_intel_crtc_clock_get()
1173 			    ((dpll &  in psb_intel_crtc_clock_get()
1177 		if (dpll & PLL_P2_DIVIDE_BY_4)  in psb_intel_crtc_clock_get()