Home
last modified time | relevance | path

Searched refs:SDRAM (Results 1 – 25 of 74) sorted by relevance

123

/linux-2.6.39/arch/arm/mach-pnx4008/
Dsleep.S48 @ clear SDRAM self-refresh bit latch
50 @ clear SDRAM self-refresh bit
57 @ set SDRAM self-refresh bit
61 @ set SDRAM self-refresh bit latch
65 @ clear SDRAM self-refresh bit latch
69 @ clear SDRAM self-refresh bit
73 @ wait for SDRAM to get into self-refresh mode
78 @ to prepare SDRAM to get out of self-refresh mode after wakeup
98 @ clear STOP mode and SDRAM self-refresh bits
101 @ wait for SDRAM to get out self-refresh mode
[all …]
/linux-2.6.39/arch/arm/mach-s3c2410/
Dsleep.S52 orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command
53 orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
64 streq r7, [ r4 ] @ SDRAM sleep command
65 streq r8, [ r5 ] @ SDRAM power-down config
/linux-2.6.39/arch/arm/mach-pxa/
Dsleep.S75 @ prepare SDRAM refresh settings
79 @ enable SDRAM self-refresh mode
121 @ prepare SDRAM refresh settings
125 @ enable SDRAM self-refresh mode
132 @ We keep the change-down close to the actual suspend on SDRAM
185 @ external accesses after SDRAM is put in self-refresh mode
191 @ put SDRAM into self-refresh
/linux-2.6.39/arch/frv/kernel/
Dhead-mmu-fr451.S40 # describe the position and layout of the SDRAM controller registers
44 # GR11 - displacement of 2nd SDRAM addr reg from GR14
45 # GR12 - displacement of 3rd SDRAM addr reg from GR14
46 # GR13 - displacement of 4th SDRAM addr reg from GR14
47 # GR14 - address of 1st SDRAM addr reg
48 # GR15 - amount to shift address by to match SDRAM addr reg
168 # determine the total SDRAM size
171 # GR25 - SDRAM size
183 sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
225 # GR25 SDRAM size [saved]
Dhead-uc-fr401.S39 # describe the position and layout of the SDRAM controller registers
43 # GR11 - displacement of 2nd SDRAM addr reg from GR14
44 # GR12 - displacement of 3rd SDRAM addr reg from GR14
45 # GR13 - displacement of 4th SDRAM addr reg from GR14
46 # GR14 - address of 1st SDRAM addr reg
47 # GR15 - amount to shift address by to match SDRAM addr reg
173 # determine the total SDRAM size
176 # GR25 - SDRAM size
188 sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
236 # GR25 SDRAM size [saved]
Dhead-uc-fr555.S38 # describe the position and layout of the SDRAM controller registers
42 # GR11 - displacement of 2nd SDRAM addr reg from GR14
43 # GR12 - displacement of 3rd SDRAM addr reg from GR14
44 # GR13 - displacement of 4th SDRAM addr reg from GR14
45 # GR14 - address of 1st SDRAM addr reg
46 # GR15 - amount to shift address by to match SDRAM addr reg
161 # determine the total SDRAM size
164 # GR25 - SDRAM size
176 sethi.p %hi(0xfff),gr17 ; unused SDRAM AMK value
220 # GR25 SDRAM size saved
Dcmode.S84 # to access SDRAM and the internal resources.
114 # (6) Execute loading the dummy for SDRAM.
117 # (7) Set '1' to the DRCN.SR bit, and change SDRAM to the
154 # (14) Release the self-refresh of SDRAM.
Dhead.inc47 __sdram_base = 0x00000000 /* base address to which SDRAM relocated */
49 __sdram_base = __page_offset /* base address to which SDRAM relocated */
Dsleep.S135 # put SDRAM in self-refresh mode
143 # Execute dummy load from SDRAM
146 # put the SDRAM into self-refresh mode
152 # wait for SDRAM to reach self-refresh mode
189 # wake SDRAM from self-refresh mode
200 # wait for the SDRAM to stabilise
/linux-2.6.39/arch/arm/mach-ep93xx/
DKconfig13 prompt "EP93xx first SDRAM bank selection"
20 first SDRAM bank at 0x00000000.
26 first SDRAM bank at 0xc0000000.
32 first SDRAM bank at 0xd0000000.
38 first SDRAM bank at 0xe0000000.
44 first SDRAM bank at 0xf0000000.
/linux-2.6.39/arch/arm/mach-at91/
Dat91sam9_alt_reset.S39 str r2, [r0, #AT91_SDRAMC_TR] @ disable SDRAM access
40 str r3, [r0, #AT91_SDRAMC_LPR] @ power down SDRAM
Dpm.h90 #warning Assuming EB1 SDRAM controller is *NOT* used
/linux-2.6.39/Documentation/video4linux/cx2341x/
Dfw-upload.txt35 - Write 0x0000001A to register 0x07FC to init the Encoder SDRAM's pre-charge.
36 - Write 0x80000640 to register 0x07F8 to init the Encoder SDRAM's refresh to 1us.
37 - Write 0x0000001A to register 0x08FC to init the Decoder SDRAM's pre-charge.
38 - Write 0x80000640 to register 0x08F8 to init the Decoder SDRAM's refresh to 1us.
Dfw-memory.txt85 0x07F8: Encoder SDRAM refresh
86 0x07FC: Encoder SDRAM pre-charge
93 0x08F8: Decoder SDRAM refresh
94 0x08FC: Decoder SDRAM pre-charge
/linux-2.6.39/arch/m32r/platforms/mappi2/
Ddot.gdbinit.vdec29 # Initialize SDRAM controller for Mappi
29 Mappi SDRAM controller initialization
33 # Initialize SDRAM controller for Mappi
54 Mappi SDRAM controller initialization
/linux-2.6.39/Documentation/frv/
Dfeatures.txt75 0xC0000000 - 0xCFFFFFFF SDRAM
90 The kernel reads the size of the SDRAM from the memory bus controller
93 The kernel initialisation code (1) adjusts the SDRAM base addresses to
94 move the SDRAM to desired address, (2) moves the kernel image down to the
95 bottom of SDRAM, (3) adjusts the bus controller registers to move I/O
118 tiled over the top of the SDRAM such that:
122 making sure no SDRAM is actually made unavailable by this approach.
125 of the SDRAM.
/linux-2.6.39/arch/cris/arch-v10/lib/
Dhw_settings.S33 ; SDRAM or EDO DRAM?
/linux-2.6.39/arch/arm/mach-lpc32xx/
Dsuspend.S53 @ Wait for SDRAM busy status to go busy and then idle
/linux-2.6.39/arch/arm/mach-omap1/
Dsleep.S77 @ prepare to put SDRAM into self-refresh manually
162 @ prepare to put SDRAM into self-refresh manually
232 @ Prepare to put SDRAM into self-refresh manually
/linux-2.6.39/Documentation/arm/SA1100/
DPangolin3 It has EISA slots for ease of configuration with SDRAM/Flash
/linux-2.6.39/arch/cris/arch-v32/mach-fs/
DKconfig51 SDRAM configuration for group 0. The value depends on the
62 SDRAM configuration for group 1. The default value is 0
71 SDRAM timing parameters. The default value is ok for
81 SDRAM command. Should be 0 unless you really know what
/linux-2.6.39/arch/frv/
DKconfig92 The arch is, however, capable of supporting up to 3GB of SDRAM.
111 will rearrange the SDRAM layout to start at this address, and move
113 sufficiently less than 0xE0000000 that the SDRAM does not intersect
116 The base address must also be aligned such that the SDRAM controller
117 can decode it. For instance, a 512MB SDRAM bank must be 512MB aligned.
/linux-2.6.39/arch/m32r/platforms/m32700ut/
Ddot.gdbinit_200MHz_16MB33 # Initialize SDRAM controller
53 SDRAM controller initialization
164 # SDRAM: 16MB
Ddot.gdbinit_300MHz_32MB33 # Initialize SDRAM controller
53 SDRAM controller initialization
164 # SDRAM: 32MB
Ddot.gdbinit_400MHz_32MB33 # Initialize SDRAM controller
53 SDRAM controller initialization
164 # SDRAM: 32MB

123