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Searched refs:S3C_CLK_DIV2 (Results 1 – 3 of 3) sorted by relevance

/linux-2.6.39/arch/arm/mach-s3c64xx/
Dclock.c658 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
669 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
679 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
689 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 },
699 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 },
709 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 },
719 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 },
Dpm.c64 SAVE_ITEM(S3C_CLK_DIV2),
/linux-2.6.39/arch/arm/mach-s3c64xx/include/mach/
Dregs-clock.h30 #define S3C_CLK_DIV2 S3C_CLKREG(0x28) macro