Searched refs:S3C_CLK_DIV0 (Results 1 – 3 of 3) sorted by relevance
405 clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask; in s3c64xx_clk_arm_get_rate()438 val = __raw_readl(S3C_CLK_DIV0); in s3c64xx_clk_arm_set_rate()441 __raw_writel(val, S3C_CLK_DIV0); in s3c64xx_clk_arm_set_rate()464 if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK) in s3c64xx_clk_doutmpll_get_rate()728 .reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 },760 clkdiv0 = __raw_readl(S3C_CLK_DIV0); in s3c6400_setup_clocks()
62 SAVE_ITEM(S3C_CLK_DIV0),
28 #define S3C_CLK_DIV0 S3C_CLKREG(0x20) macro