Searched refs:UART_MOD_CNTRL (Results 1 – 5 of 5) sorted by relevance
53 #define UART_MOD_CNTRL 0x100 /* Module Control */ macro65 if (UART16550_READ(UART_MOD_CNTRL) != 0x3) { in debugInit()66 UART16550_WRITE(UART_MOD_CNTRL, 3); in debugInit()
117 sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL); in save_core_regs()192 au_writel(0, UART0_ADDR + UART_MOD_CNTRL); au_sync(); in restore_core_regs()193 au_writel(1, UART0_ADDR + UART_MOD_CNTRL); au_sync(); in restore_core_regs()194 au_writel(3, UART0_ADDR + UART_MOD_CNTRL); au_sync(); in restore_core_regs()376 (UART_BASE + UART_MOD_CNTRL + in pm_do_freq()
68 au_writel(0x01, UART3_ADDR+UART_MOD_CNTRL); // clock enable (CE) in board_setup()70 au_writel(0x03, UART3_ADDR+UART_MOD_CNTRL); // CE and "enable" in board_setup()
753 if (au_readl(UART_MOD_CNTRL + state->port) != 0x3) {754 au_writel(3, UART_MOD_CNTRL + state->port);991 au_writel(0, UART_MOD_CNTRL + state->port);2518 if (au_readl(UART_MOD_CNTRL + state->port) != 0x3) {2519 au_writel(3, UART_MOD_CNTRL + state->port);
917 #define UART_MOD_CNTRL 0x100 /* Module Control */ macro