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Searched refs:BIT0 (Results 1 – 11 of 11) sorted by relevance

/linux-2.4.37.9/drivers/scsi/
Dtmscsim.h288 #define BIT0 0x00000001 macro
291 #define UNIT_ALLOCATED BIT0
297 #define DASD_SUPPORT BIT0
303 #define SRB_WAIT BIT0
320 #define SRB_OK BIT0
328 #define RESET_DEV BIT0
333 #define ABORT_DEV_ BIT0
342 #define AUTO_REQSENSE BIT0
382 #define SYNC_ENABLE BIT0
488 #define PARITY_CHK_ BIT0
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/linux-2.4.37.9/drivers/net/
Dmv64340_eth.h13 #define BIT0 0x00000001 macro
237 #define ETH_INTERFACE_PCM BIT0
260 #define ETH_UNICAST_PROMISCUOUS_MODE BIT0
315 #define ETH_CLASSIFY_EN BIT0
323 #define ETH_QUEUE_0_ENABLE BIT0
342 #define ETH_RIFB BIT0
364 #define ETH_SERIAL_PORT_ENABLE BIT0
417 #define ETH_ERROR_SUMMARY (BIT0)
Dcs89x0.h467 #define BIT0 1 macro
Dmv64340_eth.c385 if (eth_int_cause_ext & (BIT0 | BIT8)) in mv64340_eth_free_tx_queue()
388 if (pkt_info.cmd_sts & BIT0) { in mv64340_eth_free_tx_queue()
/linux-2.4.37.9/include/asm-arm/arch-omaha/
Dplatform.h591 #define PLD_INT_CTRL_USB BIT0 /* USB */
596 #define PLD_INT_STATUS_CF_IDE BIT0 /* CF True-IDE mode (r/w) */
603 #define PLD_WAIT_STATUS_USB BIT0 /* USB wait signal active */
624 #define PLD_CF_WP BIT0 /* r/w */
Dbits.h26 #define BIT0 0x00000001 macro
/linux-2.4.37.9/include/asm-arm/arch-integrator/
Dbits.h26 #define BIT0 0x00000001 macro
/linux-2.4.37.9/include/linux/
Dsynclink.h20 #define BIT0 0x0001 macro
/linux-2.4.37.9/drivers/char/
Dsynclinkmp.c442 #define RXRDYE BIT0
454 #define BRKE BIT0
455 #define IDLD BIT0
2119 while((status = read_reg(info,CST0)) & BIT0) in isr_rxrdy()
2550 if (status & BIT0 << shift) in synclinkmp_interrupt()
2559 if (dmastatus & BIT0 << shift) in synclinkmp_interrupt()
4051 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0))); in enable_loopback()
4054 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); in enable_loopback()
4069 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0))); in enable_loopback()
4439 RegValue |= BIT0; in async_mode()
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Dsynclink.c530 #define MISC BIT0
549 #define RXSTATUS_DATA_AVAILABLE BIT0
587 #define TXSTATUS_FIFO_EMPTY BIT0
607 #define MISCSTATUS_BRG0_ZERO BIT0
633 #define SICR_BRG0_ZERO BIT0
667 #define TXSTATUS_FIFO_EMPTY BIT0
670 #define DICR_TRANSMIT BIT0
1720 usc_OutDmaReg(info, CDIR, BIT8+BIT0 ); in mgsl_isr_transmit_dma()
5603 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_loopback()
5666 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_aux_clock()
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/linux-2.4.37.9/drivers/char/pcmcia/
Dsynclink_cs.c331 #define IRQ_RXFIFO BIT0 // receive pool full
339 #define PVR_DTR BIT0
917 #define CMD_TXRESET BIT0 // transmit reset
1425 if (gis & (BIT1 + BIT0)) { in mgslpc_isr()
3510 val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0); in loopback_enable()
3524 val = read_reg(info, CHA + MODE) | BIT0; in loopback_enable()
3577 val |= BIT0; in hdlc_mode()
3647 val |= BIT0; in hdlc_mode()
3923 val |= BIT0; in async_mode()
4001 val |= BIT0; /* 7 bits */ in async_mode()