Lines Matching refs:BIT0
530 #define MISC BIT0
549 #define RXSTATUS_DATA_AVAILABLE BIT0
587 #define TXSTATUS_FIFO_EMPTY BIT0
607 #define MISCSTATUS_BRG0_ZERO BIT0
633 #define SICR_BRG0_ZERO BIT0
667 #define TXSTATUS_FIFO_EMPTY BIT0
670 #define DICR_TRANSMIT BIT0
1720 usc_OutDmaReg(info, CDIR, BIT8+BIT0 ); in mgsl_isr_transmit_dma()
5603 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_loopback()
5666 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_aux_clock()
5672 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) ); in usc_enable_aux_clock()
6002 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) ); in usc_start_transmitter()
6687 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_async_clock()
6696 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) ); in usc_enable_async_clock()