| /linux-6.6.21/drivers/net/ethernet/cavium/thunder/ |
| D | thunder_xcv.c | 72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
87 writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
94 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
102 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
106 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
130 writeq_relaxed(cfg, xcv->reg_base + XCV_CTL); in xcv_setup_link()
135 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_setup_link()
140 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_setup_link()
143 writeq_relaxed(0x01, xcv->reg_base + XCV_BATCH_CRD_RET); in xcv_setup_link()
[all …]
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| D | nic_main.c | 90 writeq_relaxed(val, nic->reg_base + offset); in nic_reg_write()
146 writeq_relaxed(msg[0], mbx_addr); in nic_send_msg_to_vf()
147 writeq_relaxed(msg[1], mbx_addr + 8); in nic_send_msg_to_vf()
149 writeq_relaxed(msg[1], mbx_addr + 8); in nic_send_msg_to_vf()
150 writeq_relaxed(msg[0], mbx_addr); in nic_send_msg_to_vf()
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| /linux-6.6.21/arch/arm64/include/asm/ |
| D | arch_gicv3.h | 136 #define gic_write_irouter(v, c) writeq_relaxed(v, c)
138 #define gic_write_lpir(v, c) writeq_relaxed(v, c)
144 #define gits_write_baser(v, c) writeq_relaxed(v, c)
147 #define gits_write_cbaser(v, c) writeq_relaxed(v, c)
149 #define gits_write_cwriter(v, c) writeq_relaxed(v, c)
152 #define gicr_write_propbaser(v, c) writeq_relaxed(v, c)
154 #define gicr_write_pendbaser(v, c) writeq_relaxed(v, c)
157 #define gicr_write_vpropbaser(v, c) writeq_relaxed(v, c)
160 #define gicr_write_vpendbaser(v, c) writeq_relaxed(v, c)
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| /linux-6.6.21/drivers/perf/ |
| D | marvell_cn10k_ddr_pmu.c | 374 writeq_relaxed(val, pmu->base + reg); in cn10k_ddr_perf_counter_enable()
388 writeq_relaxed(val, pmu->base + DDRC_PERF_CNT_FREERUN_EN); in cn10k_ddr_perf_counter_enable()
462 writeq_relaxed(val, pmu->base + reg_offset); in cn10k_ddr_perf_event_add()
470 writeq_relaxed(val, pmu->base + DDRC_PERF_CNT_FREERUN_CTRL); in cn10k_ddr_perf_event_add()
516 writeq_relaxed(START_OP_CTRL_VAL_START, ddr_pmu->base + in cn10k_ddr_perf_pmu_enable()
524 writeq_relaxed(END_OP_CTRL_VAL_END, ddr_pmu->base + in cn10k_ddr_perf_pmu_disable()
654 writeq_relaxed(OP_MODE_CTRL_VAL_MANNUAL, ddr_pmu->base + in cn10k_ddr_perf_probe()
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| D | marvell_cn10k_tad_pmu.c | 71 writeq_relaxed(0, tad_pmu->regions[i].base + in tad_pmu_event_counter_stop()
92 writeq_relaxed(0, tad_pmu->regions[i].base + in tad_pmu_event_counter_start()
100 writeq_relaxed(reg_val, tad_pmu->regions[i].base + in tad_pmu_event_counter_start()
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| D | arm_smmuv3_pmu.c | 731 writeq_relaxed(doorbell, pmu->reg_base + SMMU_PMCG_IRQ_CFG0); in smmu_pmu_write_msi_msg()
743 writeq_relaxed(0, pmu->reg_base + SMMU_PMCG_IRQ_CFG0); in smmu_pmu_setup_msi()
782 writeq_relaxed(counter_present_mask, in smmu_pmu_reset()
784 writeq_relaxed(counter_present_mask, in smmu_pmu_reset()
786 writeq_relaxed(counter_present_mask, in smmu_pmu_reset()
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| D | arm-cmn.c | 1415 writeq_relaxed(CMN_CC_INIT, dtc->base + CMN_DT_PMCCNTR); in arm_cmn_read_cc()
1505 writeq_relaxed(le64_to_cpu(dn->event_sel_w), dn->pmu_base + CMN_PMU_EVENT_SEL); in arm_cmn_set_event_sel_lo()
1522 writeq_relaxed(CMN_CC_INIT, cmn->dtc[i].base + CMN_DT_PMCCNTR); in arm_cmn_event_start()
1532 writeq_relaxed(val, base + CMN_DTM_WPn_VAL(wp_idx)); in arm_cmn_event_start()
1533 writeq_relaxed(mask, base + CMN_DTM_WPn_MASK(wp_idx)); in arm_cmn_event_start()
1560 writeq_relaxed(0, base + CMN_DTM_WPn_MASK(wp_idx)); in arm_cmn_event_stop()
1561 writeq_relaxed(~0ULL, base + CMN_DTM_WPn_VAL(wp_idx)); in arm_cmn_event_stop()
1871 writeq_relaxed(reg, dtm->base + CMN_DTM_PMU_CONFIG); in arm_cmn_event_add()
2037 writeq_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG); in arm_cmn_init_dtm()
2040 writeq_relaxed(0, dtm->base + CMN_DTM_WPn_MASK(i)); in arm_cmn_init_dtm()
[all …]
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| /linux-6.6.21/include/linux/ |
| D | io-64-nonatomic-hi-lo.h | 54 #ifndef writeq_relaxed
55 #define writeq_relaxed hi_lo_writeq_relaxed macro
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| D | io-64-nonatomic-lo-hi.h | 54 #ifndef writeq_relaxed
55 #define writeq_relaxed lo_hi_writeq_relaxed macro
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| /linux-6.6.21/arch/mips/loongson64/ |
| D | smp.c | 144 writeq_relaxed(0, ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); in legacy_ipi_clear_buf()
160 writeq_relaxed(startargs[3], in legacy_ipi_write_buf()
162 writeq_relaxed(startargs[2], in legacy_ipi_write_buf()
164 writeq_relaxed(startargs[1], in legacy_ipi_write_buf()
166 writeq_relaxed(startargs[0], in legacy_ipi_write_buf()
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| /linux-6.6.21/arch/arm64/kernel/ |
| D | smp_spin_table.c | 92 writeq_relaxed(pa_holding_pen, release_addr); in smp_spin_table_cpu_prepare()
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| D | acpi_parking_protocol.c | 102 writeq_relaxed(__pa_symbol(secondary_entry), in acpi_parking_protocol_cpu_boot()
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| /linux-6.6.21/drivers/mailbox/ |
| D | apple-mailbox.c | 134 writeq_relaxed(msg->msg0, apple_mbox->regs + apple_mbox->hw->a2i_send0); in apple_mbox_hw_send()
135 writeq_relaxed(FIELD_PREP(APPLE_MBOX_MSG1_MSG, msg->msg1), in apple_mbox_hw_send()
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| /linux-6.6.21/arch/sh/include/asm/ |
| D | io.h | 47 #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)ioswabq(v),c)) macro
57 #define writeq(v,a) ({ wmb(); writeq_relaxed((v),(a)); })
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| /linux-6.6.21/include/asm-generic/ |
| D | io.h | 384 #if defined(writeq) && !defined(writeq_relaxed)
385 #define writeq_relaxed writeq_relaxed macro
386 static inline void writeq_relaxed(u64 value, volatile void __iomem *addr) in writeq_relaxed() function
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| /linux-6.6.21/drivers/crypto/marvell/octeontx2/ |
| D | otx2_cpt_common.h | 128 writeq_relaxed(val, reg_base + in otx2_cpt_write64()
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| /linux-6.6.21/drivers/bus/fsl-mc/ |
| D | mc-sys.c | 109 writeq_relaxed(le64_to_cpu(cmd->params[i]), &portal->params[i]); in mc_write_command()
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| /linux-6.6.21/arch/riscv/include/asm/ |
| D | mmio.h | 124 #define writeq_relaxed(v, c) ({ __io_rbw(); writeq_cpu((v), (c)); __io_raw(); }) macro
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| /linux-6.6.21/drivers/clocksource/ |
| D | timer-clint.c | 118 writeq_relaxed(clint_get_cycles64() + delta, r); in clint_clock_next_event()
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| /linux-6.6.21/drivers/hwtracing/intel_th/ |
| D | sth.c | 45 writeq_relaxed(*(u64 *)payload, dest); in sth_iowrite()
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| /linux-6.6.21/drivers/cpufreq/ |
| D | apple-soc-cpufreq.c | 156 writeq_relaxed(reg, priv->reg_base + APPLE_DVFS_CMD); in apple_soc_cpufreq_set_target()
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| /linux-6.6.21/arch/x86/include/asm/ |
| D | io.h | 100 #define writeq_relaxed(v, a) __writeq(v, a) macro
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| /linux-6.6.21/drivers/iommu/arm/arm-smmu/ |
| D | arm-smmu-nvidia.c | 93 writeq_relaxed(val, reg); in nvidia_smmu_write_reg64()
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| /linux-6.6.21/drivers/iommu/arm/arm-smmu-v3/ |
| D | arm-smmu-v3.c | 3157 writeq_relaxed(doorbell, smmu->base + cfg[0]); in arm_smmu_write_msi_msg()
3168 writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0); in arm_smmu_setup_msis()
3169 writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0); in arm_smmu_setup_msis()
3172 writeq_relaxed(0, smmu->base + ARM_SMMU_PRIQ_IRQ_CFG0); in arm_smmu_setup_msis()
3333 writeq_relaxed(smmu->strtab_cfg.strtab_base, in arm_smmu_device_reset()
3339 writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); in arm_smmu_device_reset()
3365 writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); in arm_smmu_device_reset()
3379 writeq_relaxed(smmu->priq.q.q_base, in arm_smmu_device_reset()
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| /linux-6.6.21/drivers/mmc/host/ |
| D | dw_mmc.h | 491 writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
|