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Searched refs:port_sel (Results 1 – 15 of 15) sorted by relevance

/linux-6.6.21/drivers/net/ethernet/mellanox/mlx5/core/lag/
Dport_sel.c359 struct mlx5_lag_port_sel *port_sel = &ldev->port_sel; in mlx5_lag_destroy_definers() local
362 for_each_set_bit(tt, port_sel->tt_map, MLX5_NUM_TT) { in mlx5_lag_destroy_definers()
363 if (port_sel->outer.definers[tt]) in mlx5_lag_destroy_definers()
365 port_sel->outer.definers[tt]); in mlx5_lag_destroy_definers()
366 if (port_sel->inner.definers[tt]) in mlx5_lag_destroy_definers()
368 port_sel->inner.definers[tt]); in mlx5_lag_destroy_definers()
376 struct mlx5_lag_port_sel *port_sel = &ldev->port_sel; in mlx5_lag_create_definers() local
380 for_each_set_bit(tt, port_sel->tt_map, MLX5_NUM_TT) { in mlx5_lag_create_definers()
387 port_sel->outer.definers[tt] = lag_definer; in mlx5_lag_create_definers()
389 if (!port_sel->tunnel) in mlx5_lag_create_definers()
[all …]
Dlag.h71 struct mlx5_lag_port_sel port_sel; member
/linux-6.6.21/drivers/scsi/cxlflash/
Dlunmgt.c253 lli->port_sel |= CHAN2PORTMASK(chan); in cxlflash_manage_lun()
265 lli->port_sel &= ~CHAN2PORTMASK(chan); in cxlflash_manage_lun()
266 if (lli->port_sel == 0U) in cxlflash_manage_lun()
272 __func__, lli->port_sel, chan, lli->lun_id[chan]); in cxlflash_manage_lun()
Dvlun.c577 lli->port_sel)); in grow_lxt()
850 if (lli->port_sel & (1 << k)) { in cxlflash_restore_luntable()
900 nports = get_num_ports(lli->port_sel); in init_luntable()
913 if (!(lli->port_sel & (1 << k))) in init_luntable()
926 if (!(lli->port_sel & (1 << k))) in init_luntable()
940 chan = PORTMASK2CHAN(lli->port_sel); in init_luntable()
1059 if (get_num_ports(lli->port_sel) > 1) in cxlflash_disk_virtual_open()
Dsislite.h48 u32 port_sel; /* this is a selection mask: member
523 u8 port_sel; member
Dsuperpipe.h58 u32 port_sel; /* What port to use for this LUN */ member
Dmain.c496 cmd->rcb.port_sel = CHAN2PORTMASK(sdev->channel); in send_tmf()
624 cmd->rcb.port_sel = CHAN2PORTMASK(scp->device->channel); in cxlflash_queuecommand()
1228 u64 port_sel; in afu_link_reset() local
1231 port_sel = readq_be(&afu->afu_map->global.regs.afu_port_sel); in afu_link_reset()
1232 port_sel &= ~(1ULL << port); in afu_link_reset()
1233 writeq_be(port_sel, &afu->afu_map->global.regs.afu_port_sel); in afu_link_reset()
1249 port_sel |= (1ULL << port); in afu_link_reset()
1250 writeq_be(port_sel, &afu->afu_map->global.regs.afu_port_sel); in afu_link_reset()
1253 dev_dbg(dev, "%s: returning port_sel=%016llx\n", __func__, port_sel); in afu_link_reset()
Dsuperpipe.c528 u32 port_sel) in rht_format1() argument
552 dummy.port_sel = port_sel; in rht_format1()
/linux-6.6.21/drivers/gpu/drm/i915/display/
Dintel_pps.c295 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) & in vlv_initial_pps_pipe() local
298 if (port_sel != PANEL_PORT_SELECT_VLV(port)) in vlv_initial_pps_pipe()
1471 u32 pp_on, pp_off, port_sel = 0; in pps_init_registers() local
1516 port_sel = PANEL_PORT_SELECT_VLV(port); in pps_init_registers()
1520 port_sel = PANEL_PORT_SELECT_DPA; in pps_init_registers()
1523 port_sel = PANEL_PORT_SELECT_DPC; in pps_init_registers()
1526 port_sel = PANEL_PORT_SELECT_DPD; in pps_init_registers()
1534 pp_on |= port_sel; in pps_init_registers()
1685 u32 port_sel; in assert_pps_unlocked() local
1688 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; in assert_pps_unlocked()
[all …]
/linux-6.6.21/drivers/gpu/drm/rockchip/
Drockchip_drm_vop2.c1885 u32 port_sel; in vop2_setup_layer_mixer() local
1909 port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL); in vop2_setup_layer_mixer()
1910 port_sel &= RK3568_OVL_PORT_SEL__SEL_PORT; in vop2_setup_layer_mixer()
1913 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX, in vop2_setup_layer_mixer()
1916 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX, 8); in vop2_setup_layer_mixer()
1919 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, in vop2_setup_layer_mixer()
1922 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8); in vop2_setup_layer_mixer()
1925 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT2_MUX, in vop2_setup_layer_mixer()
1928 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8); in vop2_setup_layer_mixer()
1942 port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER0; in vop2_setup_layer_mixer()
[all …]
/linux-6.6.21/drivers/ata/
Dpata_icside.c56 u8 port_sel; member
240 writeb(state->port[ap->port_no].port_sel, state->ioc_base); in pata_icside_bmdma_setup()
427 state->port[0].port_sel = sel; in pata_icside_register_v6()
428 state->port[1].port_sel = sel | 1; in pata_icside_register_v6()
/linux-6.6.21/drivers/i2c/busses/
Di2c-piix4.c392 u8 smb_en, smb_en_status, port_sel; in piix4_setup_sb800() local
482 port_sel = inb_p(SB800_PIIX4_SMB_IDX + 1); in piix4_setup_sb800()
483 piix4_port_sel_sb800 = (port_sel & 0x01) ? in piix4_setup_sb800()
/linux-6.6.21/drivers/net/ethernet/mellanox/mlx5/core/
DMakefile41 mlx5_core-$(CONFIG_MLX5_ESWITCH) += lag/mp.o lag/port_sel.o lib/geneve.o lib/port_tun.o \
/linux-6.6.21/drivers/rapidio/
Drio.c1485 u32 port_sel = RIO_INVALID_ROUTE; in rio_std_route_clr_table() local
1501 port_sel = (RIO_INVALID_ROUTE << 24) | in rio_std_route_clr_table()
1513 port_sel); in rio_std_route_clr_table()
/linux-6.6.21/drivers/net/wireless/realtek/rtw89/
Dmac.c5254 u8 port_sel = rtwvif->port; in rtw89_mac_set_csi_para_reg() local
5295 if (port_sel == 0) in rtw89_mac_set_csi_para_reg()