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Searched refs:enable_reg (Results 1 – 25 of 314) sorted by relevance

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/linux-6.6.21/drivers/clk/qcom/
Dgcc-msm8660.c45 .enable_reg = 0x34c0,
124 .enable_reg = 0x29d4,
140 .enable_reg = 0x29d4,
175 .enable_reg = 0x29f4,
191 .enable_reg = 0x29f4,
226 .enable_reg = 0x2a14,
242 .enable_reg = 0x2a14,
277 .enable_reg = 0x2a34,
293 .enable_reg = 0x2a34,
328 .enable_reg = 0x2a54,
[all …]
Dgcc-sm8250.c39 .enable_reg = 0x52018,
78 .enable_reg = 0x52018,
95 .enable_reg = 0x52018,
1062 .enable_reg = 0x9000c,
1077 .enable_reg = 0x750cc,
1097 .enable_reg = 0x770cc,
1115 .enable_reg = 0xf080,
1133 .enable_reg = 0x10080,
1153 .enable_reg = 0x52000,
1166 .enable_reg = 0xb02c,
[all …]
Dgcc-mdm9615.c64 .enable_reg = 0x34c0,
77 .enable_reg = 0x34c0,
106 .enable_reg = 0x34c0,
135 .enable_reg = 0x34c0,
206 .enable_reg = 0x29d4,
222 .enable_reg = 0x29d4,
257 .enable_reg = 0x29f4,
273 .enable_reg = 0x29f4,
308 .enable_reg = 0x2a14,
324 .enable_reg = 0x2a14,
[all …]
Dgcc-ipq806x.c49 .enable_reg = 0x34c0,
78 .enable_reg = 0x34c0,
107 .enable_reg = 0x34c0,
214 .enable_reg = 0x34c0,
432 .enable_reg = 0x29d4,
448 .enable_reg = 0x29d4,
483 .enable_reg = 0x29f4,
499 .enable_reg = 0x29f4,
534 .enable_reg = 0x2a34,
550 .enable_reg = 0x2a34,
[all …]
Dgcc-sm8150.c39 .enable_reg = 0x52000,
82 .enable_reg = 0x52000,
100 .enable_reg = 0x52000,
1095 .enable_reg = 0x90018,
1110 .enable_reg = 0x750c0,
1129 .enable_reg = 0x750c0,
1148 .enable_reg = 0x770c0,
1167 .enable_reg = 0x770c0,
1184 .enable_reg = 0xf07c,
1201 .enable_reg = 0x1007c,
[all …]
Dgcc-msm8960.c47 .enable_reg = 0x34c0,
78 .enable_reg = 0x34c0,
277 .enable_reg = 0x34c0,
369 .enable_reg = 0x29d4,
385 .enable_reg = 0x29d4,
420 .enable_reg = 0x29f4,
436 .enable_reg = 0x29f4,
471 .enable_reg = 0x2a14,
487 .enable_reg = 0x2a14,
522 .enable_reg = 0x2a34,
[all …]
Dgcc-sc8180x.c52 .enable_reg = 0x52000,
94 .enable_reg = 0x52000,
113 .enable_reg = 0x52000,
132 .enable_reg = 0x52000,
1364 .enable_reg = 0x90018,
1379 .enable_reg = 0x750c0,
1399 .enable_reg = 0x750c0,
1419 .enable_reg = 0x770c0,
1439 .enable_reg = 0x770c0,
1457 .enable_reg = 0xa6084,
[all …]
Dgcc-sc8280xp.c116 .enable_reg = 0x52028,
153 .enable_reg = 0x52028,
168 .enable_reg = 0x52028,
183 .enable_reg = 0x52028,
198 .enable_reg = 0x52028,
213 .enable_reg = 0x52028,
2529 .enable_reg = 0x52018,
2544 .enable_reg = 0x52018,
2559 .enable_reg = 0x52000,
2574 .enable_reg = 0x52018,
[all …]
Dgcc-sm6350.c38 .enable_reg = 0x52010,
99 .enable_reg = 0x52010,
138 .enable_reg = 0x52010,
798 .enable_reg = 0x3e014,
818 .enable_reg = 0x3e014,
838 .enable_reg = 0x3e014,
858 .enable_reg = 0x3e010,
878 .enable_reg = 0x52000,
893 .enable_reg = 0x17008,
909 .enable_reg = 0x17018,
[all …]
Dgcc-msm8996.c52 .enable_reg = 0x52000,
94 .enable_reg = 0x5200c,
111 .enable_reg = 0x5200c,
129 .enable_reg = 0x52000,
1180 .enable_reg = 0x0f03c,
1197 .enable_reg = 0x75038,
1214 .enable_reg = 0x6010,
1231 .enable_reg = 0x9008,
1244 .enable_reg = 0x9010,
1257 .enable_reg = 0x0f008,
[all …]
Dgcc-sm8450.c43 .enable_reg = 0x62018,
82 .enable_reg = 0x62018,
99 .enable_reg = 0x62018,
1128 .enable_reg = 0x62000,
1143 .enable_reg = 0x62000,
1158 .enable_reg = 0x870d4,
1178 .enable_reg = 0x870d4,
1198 .enable_reg = 0x49088,
1218 .enable_reg = 0x62000,
1233 .enable_reg = 0x36010,
[all …]
Dmmcc-msm8960.c195 .enable_reg = 0x0140,
210 .enable_reg = 0x0140,
246 .enable_reg = 0x0154,
261 .enable_reg = 0x0154,
297 .enable_reg = 0x0220,
312 .enable_reg = 0x0220,
354 .enable_reg = 0x0040,
369 .enable_reg = 0x0040,
387 .enable_reg = 0x0040,
422 .enable_reg = 0x0024,
[all …]
Dgcc-sm7150.c45 .enable_reg = 0x52000,
100 .enable_reg = 0x52000,
117 .enable_reg = 0x52000,
972 .enable_reg = 0x2800c,
987 .enable_reg = 0x82024,
1007 .enable_reg = 0x82024,
1025 .enable_reg = 0x8201c,
1043 .enable_reg = 0x7a050,
1063 .enable_reg = 0x52004,
1076 .enable_reg = 0xb020,
[all …]
Dgcc-sm6125.c45 .enable_reg = 0x79000,
88 .enable_reg = 0x79000,
105 .enable_reg = 0x79000,
122 .enable_reg = 0x79000,
139 .enable_reg = 0x79000,
169 .enable_reg = 0x79000,
199 .enable_reg = 0x79000,
229 .enable_reg = 0x79000,
1362 .enable_reg = 0x1d004,
1377 .enable_reg = 0x1d008,
[all …]
Dgcc-msm8998.c41 .enable_reg = 0x52000,
112 .enable_reg = 0x52000,
183 .enable_reg = 0x52000,
254 .enable_reg = 0x52000,
325 .enable_reg = 0x52000,
1221 .enable_reg = 0x8202c,
1234 .enable_reg = 0x82028,
1252 .enable_reg = 0x82024,
1270 .enable_reg = 0x48090,
1283 .enable_reg = 0x48094,
[all …]
Dgcc-sc7180.c39 .enable_reg = 0x52010,
92 .enable_reg = 0x52010,
110 .enable_reg = 0x52010,
128 .enable_reg = 0x52010,
146 .enable_reg = 0x52010,
832 .enable_reg = 0x82024,
850 .enable_reg = 0x8201c,
870 .enable_reg = 0x52000,
883 .enable_reg = 0xb020,
898 .enable_reg = 0xb080,
[all …]
Dgcc-msm8976.c74 .enable_reg = 0x45000,
107 .enable_reg = 0x45000,
144 .enable_reg = 0x45000,
191 .enable_reg = 0x45000,
222 .enable_reg = 0x45000,
1657 .enable_reg = 0x78004,
1674 .enable_reg = 0x79004,
1692 .enable_reg = 0x2008,
1710 .enable_reg = 0x2004,
1728 .enable_reg = 0x3010,
[all …]
Dgcc-msm8917.c57 .enable_reg = 0x45008,
75 .enable_reg = 0x45000,
149 .enable_reg = 0x45000,
194 .enable_reg = 0x45000,
1211 .enable_reg = 0x4500c,
1224 .enable_reg = 0x59034,
1237 .enable_reg = 0x59030,
1250 .enable_reg = 0x45004,
1263 .enable_reg = 0x45004,
1276 .enable_reg = 0x03010,
[all …]
Dgcc-sa8775p.c79 .enable_reg = 0x4b028,
116 .enable_reg = 0x4b028,
131 .enable_reg = 0x4b028,
146 .enable_reg = 0x4b028,
161 .enable_reg = 0x4b028,
176 .enable_reg = 0x4b028,
1691 .enable_reg = 0x4b000,
1706 .enable_reg = 0x810d4,
1726 .enable_reg = 0x830d4,
1746 .enable_reg = 0x830d4,
[all …]
Dgcc-ipq5332.c54 .enable_reg = 0xb000,
94 .enable_reg = 0xb000,
122 .enable_reg = 0xb000,
573 .enable_reg = 0x2907c,
616 .enable_reg = 0x2a078,
679 .enable_reg = 0x28078,
1157 .enable_reg = 0x1c00c,
1175 .enable_reg = 0x34024,
1193 .enable_reg = 0xb004,
1211 .enable_reg = 0x2024,
[all …]
Dgcc-ipq5018.c64 .enable_reg = 0x0b000,
79 .enable_reg = 0x0b000,
94 .enable_reg = 0x0b000,
109 .enable_reg = 0x0b000,
1333 .enable_reg = 0x30000,
1347 .enable_reg = 0x30018,
1362 .enable_reg = 0x30030,
1379 .enable_reg = 0x1f020,
1397 .enable_reg = 0x0b004,
1414 .enable_reg = 0x02008,
[all …]
Dgcc-sc7280.c47 .enable_reg = 0x52010,
108 .enable_reg = 0x52010,
125 .enable_reg = 0x52010,
142 .enable_reg = 0x52010,
159 .enable_reg = 0x52010,
175 .enable_reg = 0x52000,
1233 .enable_reg = 0x8c004,
1246 .enable_reg = 0x8c008,
1261 .enable_reg = 0x52000,
1276 .enable_reg = 0x52000,
[all …]
Dgcc-sdm845.c41 .enable_reg = 0x52000,
58 .enable_reg = 0x52000,
75 .enable_reg = 0x52000,
1135 .enable_reg = 0x90014,
1150 .enable_reg = 0x82028,
1170 .enable_reg = 0x82024,
1188 .enable_reg = 0x8201c,
1206 .enable_reg = 0x82020,
1224 .enable_reg = 0x7a050,
1244 .enable_reg = 0x52004,
[all …]
Dgcc-sm8350.c47 .enable_reg = 0x52018,
86 .enable_reg = 0x52018,
104 .enable_reg = 0x52018,
1243 .enable_reg = 0x52000,
1257 .enable_reg = 0x52000,
1272 .enable_reg = 0x52000,
1287 .enable_reg = 0x750cc,
1307 .enable_reg = 0x750cc,
1327 .enable_reg = 0x770cc,
1347 .enable_reg = 0x770cc,
[all …]
/linux-6.6.21/arch/arm/mach-omap1/
Dclock.c49 unsigned int val = __raw_readl(clk->enable_reg); in omap1_uart_recalc()
194 regval32 = __raw_readl(clk->enable_reg); in omap1_clk_is_enabled()
196 regval32 = __raw_readw(clk->enable_reg); in omap1_clk_is_enabled()
395 val |= __raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit); in omap1_set_uart_rate()
396 __raw_writel(val, clk->enable_reg); in omap1_set_uart_rate()
422 ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd; in omap1_set_ext_clk_rate()
423 __raw_writew(ratio_bits, clk->enable_reg); in omap1_set_ext_clk_rate()
489 ratio_bits = __raw_readw(clk->enable_reg) & ~1; in omap1_init_ext_clk()
490 __raw_writew(ratio_bits, clk->enable_reg); in omap1_init_ext_clk()
534 if (unlikely(clk->enable_reg == NULL)) { in omap1_clk_enable_generic()
[all …]

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