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Searched refs:chid (Results 1 – 25 of 75) sorted by relevance

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/linux-6.6.21/drivers/gpu/drm/nouveau/nvkm/engine/fifo/ !
Dchid.c25 nvkm_chid_put(struct nvkm_chid *chid, int id, spinlock_t *data_lock) in nvkm_chid_put() argument
28 spin_lock_irq(&chid->lock); in nvkm_chid_put()
30 chid->data[id] = NULL; in nvkm_chid_put()
32 clear_bit(id, chid->used); in nvkm_chid_put()
33 spin_unlock_irq(&chid->lock); in nvkm_chid_put()
38 nvkm_chid_get(struct nvkm_chid *chid, void *data) in nvkm_chid_get() argument
42 spin_lock_irq(&chid->lock); in nvkm_chid_get()
43 cid = find_first_zero_bit(chid->used, chid->nr); in nvkm_chid_get()
44 if (cid < chid->nr) { in nvkm_chid_get()
45 set_bit(cid, chid->used); in nvkm_chid_get()
[all …]
Drunl.c185 struct nvkm_chid *chid = runl->chid; in nvkm_runl_chan_get_inst() local
190 spin_lock_irqsave(&chid->lock, flags); in nvkm_runl_chan_get_inst()
191 for_each_set_bit(id, chid->used, chid->nr) { in nvkm_runl_chan_get_inst()
192 chan = chid->data[id]; in nvkm_runl_chan_get_inst()
197 spin_unlock(&chid->lock); in nvkm_runl_chan_get_inst()
202 spin_unlock_irqrestore(&chid->lock, flags); in nvkm_runl_chan_get_inst()
209 struct nvkm_chid *chid = runl->chid; in nvkm_runl_chan_get_chid() local
213 spin_lock_irqsave(&chid->lock, flags); in nvkm_runl_chan_get_chid()
214 if (!WARN_ON(id >= chid->nr)) { in nvkm_runl_chan_get_chid()
215 chan = chid->data[id]; in nvkm_runl_chan_get_chid()
[all …]
Dnv04.c49 u32 chid; in nv04_chan_stop() local
56 chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & fifo->chid->mask; in nv04_chan_stop()
57 if (chid == chan->id) { in nv04_chan_stop()
80 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->chid->mask); in nv04_chan_stop()
274 nv04_fifo_swmthd(struct nvkm_device *device, u32 chid, u32 addr, u32 data) in nv04_fifo_swmthd() argument
293 handled = nvkm_sw_mthd(sw, chid, subc, mthd, data); in nv04_fifo_swmthd()
303 nv04_fifo_intr_cache_error(struct nvkm_fifo *fifo, u32 chid, u32 get) in nv04_fifo_intr_cache_error() argument
329 !nv04_fifo_swmthd(device, chid, mthd, data)) { in nv04_fifo_intr_cache_error()
330 chan = nvkm_chan_get_chid(&fifo->engine, chid, &flags); in nv04_fifo_intr_cache_error()
333 chid, chan ? chan->name : "unknown", in nv04_fifo_intr_cache_error()
[all …]
Dnv40.c131 int chid; in nv40_ectx_bind() local
155 chid = nvkm_rd32(device, 0x003204) & (fifo->chid->nr - 1); in nv40_ectx_bind()
156 if (chid == chan->id) in nv40_ectx_bind()
221 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->chid->mask); in nv40_fifo_init()
Dbase.c181 case NV_DEVICE_HOST_CHANNELS: *data = fifo->chid ? fifo->chid->nr : 0; return 0; in nvkm_fifo_info()
223 if (!fifo->chid) { in nvkm_fifo_info()
226 *data = runl->chid->nr; in nvkm_fifo_info()
307 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, fifo->chid->nr * in nvkm_fifo_oneinit()
348 nvkm_chid_unref(&fifo->chid); in nvkm_fifo_dtor()
Dga100.c197 u32 chid = nvkm_rd32(device, 0x040120 + (runq->id * 0x0800)) & runl->chid->mask; in ga100_runq_intr_1() local
201 RUNQ_ERROR(runq, "CTXNOTVALID chid:%d", chid); in ga100_runq_intr_1()
202 chan = nvkm_runl_chan_get_chid(runl, chid, &flags); in ga100_runq_intr_1()
236 u32 chid = nvkm_rd32(device, 0x040120 + (runq->id * 0x0800)) & runl->chid->mask; in ga100_runq_intr_0() local
241 chan = nvkm_runl_chan_get_chid(runl, chid, &flags); in ga100_runq_intr_0()
Dgf100.c243 u8 chid; member
255 status->chid = (stat & 0x0000007f); in gf100_engn_status()
258 stat, status->busy, status->save, status->unk0, status->unk1, status->chid); in gf100_engn_status()
269 return status.chid; in gf100_engn_cxid()
318 u32 chid = nvkm_rd32(device, 0x040120 + (runq->id * 0x2000)) & runq->fifo->chid->mask; in gf100_runq_intr() local
328 if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data)) in gf100_runq_intr()
335 chan = nvkm_chan_get_chid(&runq->fifo->engine, chid, &flags); in gf100_runq_intr()
338 runq->id, show, msg, chid, chan ? chan->inst->addr : 0, in gf100_runq_intr()
941 return nvkm_chid_new(&nvkm_chan_event, &fifo->engine.subdev, nr, 0, nr, &fifo->chid); in gf100_fifo_chid_ctor()
Dgv100.c146 gv100_runq_intr_1_ctxnotvalid(struct nvkm_runq *runq, int chid) in gv100_runq_intr_1_ctxnotvalid() argument
153 RUNQ_ERROR(runq, "CTXNOTVALID chid:%d", chid); in gv100_runq_intr_1_ctxnotvalid()
155 chan = nvkm_chan_get_chid(&fifo->engine, chid, &flags); in gv100_runq_intr_1_ctxnotvalid()
/linux-6.6.21/drivers/gpu/drm/nouveau/nvkm/core/ !
Dramht.c27 nvkm_ramht_hash(struct nvkm_ramht *ramht, int chid, u32 handle) in nvkm_ramht_hash() argument
36 hash ^= chid << (ramht->bits - 4); in nvkm_ramht_hash()
41 nvkm_ramht_search(struct nvkm_ramht *ramht, int chid, u32 handle) in nvkm_ramht_search() argument
45 co = ho = nvkm_ramht_hash(ramht, chid, handle); in nvkm_ramht_search()
47 if (ramht->data[co].chid == chid) { in nvkm_ramht_search()
61 int chid, int addr, u32 handle, u32 context) in nvkm_ramht_update() argument
68 data->chid = chid; in nvkm_ramht_update()
75 data->chid = -1; in nvkm_ramht_update()
108 int chid, int addr, u32 handle, u32 context) in nvkm_ramht_insert() argument
112 if (nvkm_ramht_search(ramht, chid, handle)) in nvkm_ramht_insert()
[all …]
/linux-6.6.21/drivers/gpu/drm/nouveau/nvkm/engine/disp/ !
Dgp102.c38 int ctrl = chan->chid.ctrl; in gp102_disp_dmac_init()
39 int user = chan->chid.user; in gp102_disp_dmac_init()
148 gp102_disp_intr_error(struct nvkm_disp *disp, int chid) in gp102_disp_intr_error() argument
152 u32 mthd = nvkm_rd32(device, 0x6111f0 + (chid * 12)); in gp102_disp_intr_error()
153 u32 data = nvkm_rd32(device, 0x6111f4 + (chid * 12)); in gp102_disp_intr_error()
154 u32 unkn = nvkm_rd32(device, 0x6111f8 + (chid * 12)); in gp102_disp_intr_error()
157 chid, (mthd & 0x0000ffc), data, mthd, unkn); in gp102_disp_intr_error()
159 if (chid < ARRAY_SIZE(disp->chan)) { in gp102_disp_intr_error()
162 nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR); in gp102_disp_intr_error()
169 nvkm_wr32(device, 0x61009c, (1 << chid)); in gp102_disp_intr_error()
[all …]
Dgf119.c506 const u32 mask = 0x00000001 << chan->chid.user; in gf119_disp_chan_intr()
521 int ctrl = chan->chid.ctrl; in gf119_disp_pioc_fini()
522 int user = chan->chid.user; in gf119_disp_pioc_fini()
540 int ctrl = chan->chid.ctrl; in gf119_disp_pioc_init()
541 int user = chan->chid.user; in gf119_disp_pioc_init()
569 return nvkm_ramht_insert(chan->disp->ramht, object, chan->chid.user, -9, handle, in gf119_disp_dmac_bind()
570 chan->chid.user << 27 | 0x00000001); in gf119_disp_dmac_bind()
578 int ctrl = chan->chid.ctrl; in gf119_disp_dmac_fini()
579 int user = chan->chid.user; in gf119_disp_dmac_fini()
600 int ctrl = chan->chid.ctrl; in gf119_disp_dmac_init()
[all …]
Dgv100.c335 return 0x690000 + ((chan->chid.user - 1) * 0x1000); in gv100_disp_chan_user()
342 const u32 soff = (chan->chid.ctrl - 1) * 0x04; in gv100_disp_dmac_idle()
355 return nvkm_ramht_insert(chan->disp->ramht, object, chan->chid.user, -9, handle, in gv100_disp_dmac_bind()
356 chan->chid.user << 25 | 0x00000040); in gv100_disp_dmac_bind()
363 const u32 uoff = (chan->chid.ctrl - 1) * 0x1000; in gv100_disp_dmac_fini()
364 const u32 coff = chan->chid.ctrl * 0x04; in gv100_disp_dmac_fini()
376 const u32 uoff = (chan->chid.ctrl - 1) * 0x1000; in gv100_disp_dmac_init()
377 const u32 poff = chan->chid.ctrl * 0x10; in gv100_disp_dmac_init()
378 const u32 coff = chan->chid.ctrl * 0x04; in gv100_disp_dmac_init()
557 const u32 soff = (chan->chid.ctrl - 1) * 0x04; in gv100_disp_curs_idle()
[all …]
Dnv50.c468 mthd->name, chan->chid.user); in nv50_disp_chan_mthd()
504 nv50_disp_chan_uevent_send(struct nvkm_disp *disp, int chid) in nv50_disp_chan_uevent_send() argument
506 nvkm_event_ntfy(&disp->uevent, chid, NVKM_DISP_EVENT_CHAN_AWAKEN); in nv50_disp_chan_uevent_send()
519 return 0x640000 + (chan->chid.user * 0x1000); in nv50_disp_chan_user()
526 const u32 mask = 0x00010001 << chan->chid.user; in nv50_disp_chan_intr()
527 const u32 data = en ? 0x00010000 << chan->chid.user : 0x00000000; in nv50_disp_chan_intr()
537 int ctrl = chan->chid.ctrl; in nv50_disp_pioc_fini()
538 int user = chan->chid.user; in nv50_disp_pioc_fini()
556 int ctrl = chan->chid.ctrl; in nv50_disp_pioc_init()
557 int user = chan->chid.user; in nv50_disp_pioc_init()
[all …]
Dchan.c178 if (disp->chan[chan->chid.user] == chan) in nvkm_disp_chan_dtor()
179 disp->chan[chan->chid.user] = NULL; in nvkm_disp_chan_dtor()
230 chan->chid.ctrl = user->ctrl + args->v0.id; in nvkm_disp_chan_new_()
231 chan->chid.user = user->user + args->v0.id; in nvkm_disp_chan_new_()
241 if (disp->chan[chan->chid.user]) { in nvkm_disp_chan_new_()
245 disp->chan[chan->chid.user] = chan; in nvkm_disp_chan_new_()
/linux-6.6.21/drivers/dma/qcom/ !
Dgpi.c91 #define GPII_n_CH_CMD(opcode, chid) \ argument
93 FIELD_PREP(GPII_n_CH_CMD_CHID, chid))
140 #define GPII_n_EV_CMD(opcode, chid) \ argument
142 FIELD_PREP(GPII_n_EV_CMD_CHID, chid))
246 u8 chid; member
257 u8 chid; member
267 u8 chid; member
487 u32 chid; member
689 u32 chid = MAX_CHANNELS_PER_GPII; in gpi_send_cmd() local
697 chid = gchan->chid; in gpi_send_cmd()
[all …]
/linux-6.6.21/drivers/gpu/drm/nouveau/include/nvkm/core/ !
Dramht.h9 int chid; member
26 int chid, int addr, u32 handle, u32 context);
29 nvkm_ramht_search(struct nvkm_ramht *, int chid, u32 handle);
/linux-6.6.21/drivers/bus/mhi/ !
Dcommon.h126 #define MHI_TRE_CMD_RESET_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \ argument
133 #define MHI_TRE_CMD_STOP_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \ argument
140 #define MHI_TRE_CMD_START_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \ argument
152 #define MHI_TRE_EV_DWORD1(chid, type) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \ argument
/linux-6.6.21/drivers/gpu/drm/nouveau/nvkm/engine/gr/ !
Dnv20.c24 nvkm_wo32(gr->ctxtab, chan->chid * 4, inst >> 4); in nv20_gr_chan_init()
36 int chid = -1; in nv20_gr_chan_fini() local
40 chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24; in nv20_gr_chan_fini()
41 if (chan->chid == chid) { in nv20_gr_chan_fini()
54 nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000); in nv20_gr_chan_fini()
86 chan->chid = fifoch->id; in nv20_gr_chan_new()
96 nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24)); in nv20_gr_chan_new()
190 u32 chid = (addr & 0x01f00000) >> 20; in nv20_gr_intr() local
199 chan = nvkm_chan_get_chid(&gr->base.engine, chid, &flags); in nv20_gr_intr()
211 show, msg, nsource, src, nstatus, sta, chid, in nv20_gr_intr()
Dnv10.c402 int chid; member
552 int chid = nvkm_rd32(device, 0x400148) >> 24; in nv10_gr_channel() local
553 if (chid < ARRAY_SIZE(gr->chan)) in nv10_gr_channel()
554 chan = gr->chan[chid]; in nv10_gr_channel()
812 nv10_gr_load_dma_vtxbuf(struct nv10_gr_chan *chan, int chid, u32 inst) in nv10_gr_load_dma_vtxbuf() argument
861 0x2c000000 | chid << 20 | subchan << 16 | 0x18c); in nv10_gr_load_dma_vtxbuf()
883 nv10_gr_load_context(struct nv10_gr_chan *chan, int chid) in nv10_gr_load_context() argument
901 nv10_gr_load_dma_vtxbuf(chan, chid, inst); in nv10_gr_load_context()
904 nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24); in nv10_gr_load_context()
937 int chid; in nv10_gr_context_switch() local
[all …]
Dnv04.c362 int chid; member
1077 int chid = nvkm_rd32(device, NV04_PGRAPH_CTX_USER) >> 24; in nv04_gr_channel() local
1078 if (chid < ARRAY_SIZE(gr->chan)) in nv04_gr_channel()
1079 chan = gr->chan[chid]; in nv04_gr_channel()
1085 nv04_gr_load_context(struct nv04_gr_chan *chan, int chid) in nv04_gr_load_context() argument
1094 nvkm_mask(device, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24); in nv04_gr_load_context()
1119 int chid; in nv04_gr_context_switch() local
1129 chid = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f; in nv04_gr_context_switch()
1130 next = gr->chan[chid]; in nv04_gr_context_switch()
1132 nv04_gr_load_context(next, chid); in nv04_gr_context_switch()
[all …]
Dnv50.c396 int chid, u64 inst, const char *name) in nv50_gr_trap_handler() argument
436 chid, inst, name, subc, class, mthd, in nv50_gr_trap_handler()
461 "40084c %08x\n", chid, inst, name, in nv50_gr_trap_handler()
638 int chid = -1; in nv50_gr_intr() local
643 chid = chan->id; in nv50_gr_intr()
655 if (!nv50_gr_trap_handler(gr, show, chid, (u64)inst << 12, name)) in nv50_gr_intr()
668 stat, msg, chid, (u64)inst << 12, name, in nv50_gr_intr()
Dnv2a.c32 chan->chid = fifoch->id; in nv2a_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24)); in nv2a_gr_chan_new()
Dnv35.c32 chan->chid = fifoch->id; in nv35_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv35_gr_chan_new()
/linux-6.6.21/Documentation/ABI/testing/ !
Dsysfs-platform-hidma1 What: /sys/devices/platform/hidma-*/chid
2 /sys/devices/platform/QCOM8061:*/chid
/linux-6.6.21/drivers/gpu/drm/nouveau/nvkm/engine/sw/ !
Dbase.c30 nvkm_sw_mthd(struct nvkm_sw *sw, int chid, int subc, u32 mthd, u32 data) in nvkm_sw_mthd() argument
38 if (chan->fifo->id == chid) { in nvkm_sw_mthd()

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