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Searched refs:IS_ALDERLAKE_P (Results 1 – 24 of 24) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/i915/display/
Dintel_psr.c736 if (DISPLAY_VER(dev_priv) <= 13 && !IS_ALDERLAKE_P(dev_priv)) in hsw_activate_psr2()
753 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { in hsw_activate_psr2()
807 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) in transcoder_has_psr2()
887 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) in dc3co_is_pipe_port_compatible()
923 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) in tgl_dc3co_exitline_compute_config()
985 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) in psr2_granularity_check()
1091 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { in intel_psr2_config_valid()
1114 (DISPLAY_VER(dev_priv) <= 13 && !IS_ALDERLAKE_P(dev_priv))) { in intel_psr2_config_valid()
1149 IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { in intel_psr2_config_valid()
1467 else if (IS_ALDERLAKE_P(dev_priv)) in intel_psr_enable_source()
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Dintel_display_device.h59 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
Dintel_dmc.c960 if (IS_ALDERLAKE_P(i915)) in dmc_fallback_path()
1046 } else if (IS_ALDERLAKE_P(i915)) { in intel_dmc_init()
1215 str_yes_no(IS_ALDERLAKE_P(i915) || in intel_dmc_debugfs_status_show()
Dintel_fb.c1233 return (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) && in intel_fb_needs_pot_stride_remap()
1373 if ((IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) && in plane_view_scanout_stride()
1581 (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)) in intel_fb_view_init()
Dskl_universal_plane.c2177 if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) in skl_plane_has_rc_ccs()
2203 if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) in gen12_plane_has_mc_ccs()
2218 if (DISPLAY_VER(i915) < 13 || IS_ALDERLAKE_P(i915)) in skl_get_plane_caps()
Dintel_ddi.c344 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) { in intel_ddi_init_dp_buf_reg()
1366 if (IS_ALDERLAKE_P(dev_priv)) { in tgl_dkl_phy_set_signal_levels()
2270 if (IS_ALDERLAKE_P(i915)) in intel_ddi_splitter_pipe_mask()
3228 } else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) { in intel_enable_ddi_hdmi()
3498 if (IS_ALDERLAKE_P(dev_priv) && in intel_ddi_prepare_link_retrain()
4691 return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) && in assert_has_icl_dsi()
Dintel_dpll_mgr.c209 if (IS_ALDERLAKE_P(i915)) in intel_tc_pll_enable_reg()
2467 IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) && in ehl_combo_pll_div_frac_wa_needed()
3789 if (!(IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) || in adlp_cmtg_clock_gating_wa()
4148 else if (IS_ALDERLAKE_P(dev_priv)) in intel_shared_dpll_init()
Dicl_dsi.c352 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { in gen11_dsi_program_esc_clk_div()
373 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { in gen11_dsi_program_esc_clk_div()
Dintel_display_power.c1139 if (IS_ALDERLAKE_P(dev_priv)) in gen12_dbuf_slices_config()
1153 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) in icl_mbus_init()
Dintel_bw.c670 else if (IS_ALDERLAKE_P(dev_priv)) in intel_bw_init_hw()
Dintel_ddi_buf_trans.c1716 } else if (IS_ALDERLAKE_P(i915)) { in intel_ddi_buf_trans_init()
Dintel_cdclk.c3580 } else if (IS_ALDERLAKE_P(dev_priv)) { in intel_init_cdclk_hooks()
3582 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { in intel_init_cdclk_hooks()
Dintel_display_power_well.c348 if (IS_ALDERLAKE_P(dev_priv) && pg == SKL_PG1) in hsw_power_well_enable()
Dskl_watermark.c3602 else if (IS_ALDERLAKE_P(i915)) in intel_mbus_dbox_update()
3611 } else if (IS_ALDERLAKE_P(i915)) { in intel_mbus_dbox_update()
Dintel_bios.c2197 if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) { in map_ddc_pin()
Dintel_display.c1754 else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12)) in intel_phy_is_combo()
1770 else if (IS_ALDERLAKE_P(dev_priv) || IS_METEORLAKE(dev_priv)) in intel_phy_is_tc()
Dintel_dp.c500 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) || in intel_dp_set_source_rates()
/linux-6.6.21/drivers/gpu/drm/i915/soc/
Dintel_pch.c141 !IS_ALDERLAKE_P(dev_priv)); in intel_pch_type()
178 else if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) in intel_virt_detect_pch()
/linux-6.6.21/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_hwconfig.c97 if (IS_ALDERLAKE_P(i915) && !IS_ALDERLAKE_P_N(i915)) in has_table()
/linux-6.6.21/drivers/gpu/drm/i915/gt/
Dintel_tlb.c90 IS_ALDERLAKE_P(i915))) in mmio_invalidate_full()
Dintel_workarounds.c2517 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) || in rcs_engine_wa_init()
2532 if (IS_ALDERLAKE_P(i915) || IS_DG2(i915) || IS_ALDERLAKE_S(i915) || in rcs_engine_wa_init()
2545 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || in rcs_engine_wa_init()
2555 if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) { in rcs_engine_wa_init()
2570 IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) { in rcs_engine_wa_init()
/linux-6.6.21/drivers/gpu/drm/i915/
Dintel_step.c201 } else if (IS_ALDERLAKE_P(i915)) { in intel_step_init()
Dintel_clock_gating.c854 else if (IS_ALDERLAKE_P(i915)) in intel_clock_gating_hooks_init()
Di915_drv.h570 #define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P) macro