Searched refs:DISP_CC_MDSS_CORE_BCR (Results 1 – 23 of 23) sorted by relevance
| /linux-6.6.21/include/dt-bindings/clock/ ! |
| D | qcom,dispcc-qcm2290.h | 36 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| D | qcom,sm6375-dispcc.h | 36 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| D | qcom,dispcc-sm8250.h | 70 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| D | qcom,dispcc-sm8350.h | 70 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| D | qcom,dispcc-sm8150.h | 70 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| D | qcom,dispcc-sc8280xp.h | 93 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| D | qcom,sm8450-dispcc.h | 95 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| D | qcom,sm8550-dispcc.h | 93 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| /linux-6.6.21/Documentation/devicetree/bindings/display/msm/ ! |
| D | qcom,sc8280xp-mdss.yaml | 73 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
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| D | qcom,sm8350-mdss.yaml | 96 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| D | qcom,sm8550-mdss.yaml | 90 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| D | qcom,sm8450-mdss.yaml | 90 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| /linux-6.6.21/drivers/clk/qcom/ ! |
| D | dispcc-qcm2290.c | 449 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
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| D | dispcc-sm6375.c | 544 [DISP_CC_MDSS_CORE_BCR] = { 0x1000 },
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| D | dispcc-sm8250.c | 1219 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
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| D | dispcc-sm8450.c | 1731 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
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| D | dispcc-sm8550.c | 1724 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
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| D | dispcc-sc8280xp.c | 3047 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
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| /linux-6.6.21/arch/arm64/boot/dts/qcom/ ! |
| D | sc8280xp.dtsi | 3470 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
4578 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>;
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| D | sm8350.dtsi | 2435 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| D | sc8180x.dtsi | 2692 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| D | sm8550.dtsi | 2447 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| D | sm8450.dtsi | 2737 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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