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Searched refs:vgpu_vreg_t (Results 1 – 11 of 11) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/i915/gvt/
Ddisplay.c63 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE)) in edp_pipe_is_enabled()
79 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) in pipe_is_enabled()
181 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= in emulate_monitor_status_change()
187 vgpu_vreg_t(vgpu, PIPECONF(pipe)) &= in emulate_monitor_status_change()
189 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE; in emulate_monitor_status_change()
190 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; in emulate_monitor_status_change()
191 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK; in emulate_monitor_status_change()
192 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE; in emulate_monitor_status_change()
196 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &= in emulate_monitor_status_change()
200 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= in emulate_monitor_status_change()
[all …]
Dmmio.c252 vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0; in intel_vgpu_reset_mmio()
255 vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0; in intel_vgpu_reset_mmio()
258 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; in intel_vgpu_reset_mmio()
261 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= in intel_vgpu_reset_mmio()
263 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in intel_vgpu_reset_mmio()
265 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= in intel_vgpu_reset_mmio()
267 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= in intel_vgpu_reset_mmio()
269 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= in intel_vgpu_reset_mmio()
271 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= in intel_vgpu_reset_mmio()
273 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= in intel_vgpu_reset_mmio()
[all …]
Dfb_decoder.c152 u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask; in intel_vgpu_get_stride()
214 val = vgpu_vreg_t(vgpu, DSPCNTR(pipe)); in intel_vgpu_decode_primary_plane()
248 plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; in intel_vgpu_decode_primary_plane()
264 plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >> in intel_vgpu_decode_primary_plane()
267 plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & in intel_vgpu_decode_primary_plane()
271 val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe)); in intel_vgpu_decode_primary_plane()
345 val = vgpu_vreg_t(vgpu, CURCNTR(pipe)); in intel_vgpu_decode_cursor_plane()
371 plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK; in intel_vgpu_decode_cursor_plane()
382 val = vgpu_vreg_t(vgpu, CURPOS(pipe)); in intel_vgpu_decode_cursor_plane()
388 plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)); in intel_vgpu_decode_cursor_plane()
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Dvgpu.c43 vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1; in populate_pvinfo_page()
44 vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0; in populate_pvinfo_page()
45 vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0; in populate_pvinfo_page()
46 vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id; in populate_pvinfo_page()
48 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT; in populate_pvinfo_page()
49 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION; in populate_pvinfo_page()
50 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT; in populate_pvinfo_page()
52 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) = in populate_pvinfo_page()
54 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) = in populate_pvinfo_page()
56 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) = in populate_pvinfo_page()
[all …]
Dedid.c130 vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY; in reset_gmbus_controller()
132 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER; in reset_gmbus_controller()
164 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE; in gmbus0_mmio_write()
165 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE; in gmbus0_mmio_write()
171 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER; in gmbus0_mmio_write()
173 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER; in gmbus0_mmio_write()
200 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT; in gmbus1_mmio_write()
201 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY; in gmbus1_mmio_write()
249 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE; in gmbus1_mmio_write()
261 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE; in gmbus1_mmio_write()
[all …]
Dmmio_context.c228 *cs++ = vgpu_vreg_t(vgpu, mmio->reg) | (mmio->mask << 16); in restore_context_mmio_for_inhibit()
258 *cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index)); in restore_render_mocs_control_for_inhibit()
285 *cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index)); in restore_render_mocs_l3cc_for_inhibit()
391 vgpu_vreg_t(vgpu, reg) = 0; in handle_tlb_pending_event()
425 old_v = vgpu_vreg_t(pre, offset); in switch_mocs()
429 new_v = vgpu_vreg_t(next, offset); in switch_mocs()
443 old_v = vgpu_vreg_t(pre, l3_offset); in switch_mocs()
447 new_v = vgpu_vreg_t(next, l3_offset); in switch_mocs()
498 vgpu_vreg_t(pre, mmio->reg) = in switch_mmio()
501 vgpu_vreg_t(pre, mmio->reg) &= in switch_mmio()
[all …]
Dhandlers.c340 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; in gdrst_mmio_write()
372 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; in pch_pp_control_mmio_write()
373 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; in pch_pp_control_mmio_write()
374 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; in pch_pp_control_mmio_write()
375 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; in pch_pp_control_mmio_write()
378 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= in pch_pp_control_mmio_write()
457 u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)); in bdw_vgpu_get_dp_bitrate()
471 switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) { in bdw_vgpu_get_dp_bitrate()
483 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL)); in bdw_vgpu_get_dp_bitrate()
495 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1)); in bdw_vgpu_get_dp_bitrate()
[all …]
Dcmd_parser.c1396 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0); in gen8_check_mi_display_flip()
1397 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & in gen8_check_mi_display_flip()
1400 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) & in gen8_check_mi_display_flip()
1402 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10; in gen8_check_mi_display_flip()
1421 set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12), in gen8_update_plane_mmio_from_mi_display_flip()
1424 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0), in gen8_update_plane_mmio_from_mi_display_flip()
1426 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10), in gen8_update_plane_mmio_from_mi_display_flip()
1429 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6), in gen8_update_plane_mmio_from_mi_display_flip()
1431 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10), in gen8_update_plane_mmio_from_mi_display_flip()
1436 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(info->pipe))++; in gen8_update_plane_mmio_from_mi_display_flip()
Dscheduler.c653 vgpu_vreg_t(workload->vgpu, RING_START(workload->engine->mmio_base)) = in update_vreg_in_ctx()
971 vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail; in update_guest_context()
972 vgpu_vreg_t(vgpu, RING_HEAD(ring_base)) = head; in update_guest_context()
Dgvt.h461 #define vgpu_vreg_t(vgpu, reg) \ macro
Dgtt.c1077 u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) & in vgpu_ips_enabled()