340 			vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;  in gdrst_mmio_write()
372 		vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON;  in pch_pp_control_mmio_write()
373 		vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;  in pch_pp_control_mmio_write()
374 		vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;  in pch_pp_control_mmio_write()
375 		vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;  in pch_pp_control_mmio_write()
378 		vgpu_vreg_t(vgpu, PCH_PP_STATUS) &=  in pch_pp_control_mmio_write()
457 	u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port));  in bdw_vgpu_get_dp_bitrate()
471 		switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) {  in bdw_vgpu_get_dp_bitrate()
483 				    vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL));  in bdw_vgpu_get_dp_bitrate()
495 			wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1));  in bdw_vgpu_get_dp_bitrate()
497 			wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL2));  in bdw_vgpu_get_dp_bitrate()
521 			    vgpu->id, port_name(port), vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)));  in bdw_vgpu_get_dp_bitrate()
557 	temp = vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port));  in bxt_vgpu_get_dp_bitrate()
566 				 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0))) << 22;  in bxt_vgpu_get_dp_bitrate()
567 	if (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 3)) & PORT_PLL_M2_FRAC_ENABLE)  in bxt_vgpu_get_dp_bitrate()
569 					  vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2)));  in bxt_vgpu_get_dp_bitrate()
571 				vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1)));  in bxt_vgpu_get_dp_bitrate()
573 				 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));  in bxt_vgpu_get_dp_bitrate()
575 				 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));  in bxt_vgpu_get_dp_bitrate()
599 	if (!(vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)) &&  in skl_vgpu_get_dp_bitrate()
600 	    (vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_SEL_OVERRIDE(port))) {  in skl_vgpu_get_dp_bitrate()
601 		dpll_id += (vgpu_vreg_t(vgpu, DPLL_CTRL2) &  in skl_vgpu_get_dp_bitrate()
611 	switch ((vgpu_vreg_t(vgpu, DPLL_CTRL1) &  in skl_vgpu_get_dp_bitrate()
648 	port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &  in vgpu_update_refresh_rate()
664 	link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A));  in vgpu_update_refresh_rate()
665 	link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A));  in vgpu_update_refresh_rate()
668 	htotal = (vgpu_vreg_t(vgpu, HTOTAL(TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);  in vgpu_update_refresh_rate()
669 	vtotal = (vgpu_vreg_t(vgpu, VTOTAL(TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);  in vgpu_update_refresh_rate()
797 			vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E))  in ddi_buf_ctl_mmio_write()
815 	u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));  in fdi_auto_training_started()
817 	u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));  in fdi_auto_training_started()
858 	if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits)  in check_fdi_rx_train_status()
861 	if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)  in check_fdi_rx_train_status()
863 		&& ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)  in check_fdi_rx_train_status()
920 		vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;  in update_fdi_rx_iir_status()
926 		vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;  in update_fdi_rx_iir_status()
930 			vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |=  in update_fdi_rx_iir_status()
951 		vgpu_vreg_t(vgpu, status_reg) |= (1 << 25);  in dp_tp_ctl_mmio_write()
1010 	vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);  in pri_surf_mmio_write()
1012 	vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;  in pri_surf_mmio_write()
1014 	if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP)  in pri_surf_mmio_write()
1032 	vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);  in spr_surf_mmio_write()
1034 	if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP)  in spr_surf_mmio_write()
1053 		vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);  in reg50080_mmio_write()
1054 		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;  in reg50080_mmio_write()
1056 		vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);  in reg50080_mmio_write()
1390 	if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>  in sbi_data_mmio_read()
1392 		unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &  in sbi_data_mmio_read()
1417 	if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>  in sbi_ctl_mmio_write()
1419 		unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &  in sbi_ctl_mmio_write()
1423 					   vgpu_vreg_t(vgpu, SBI_DATA));  in sbi_ctl_mmio_write()
1677 	u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA);  in mailbox_write()
1873 		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=  in bxt_gt_disp_pwron_write()
1875 		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=  in bxt_gt_disp_pwron_write()
1880 		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=  in bxt_gt_disp_pwron_write()
1882 		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=  in bxt_gt_disp_pwron_write()