Searched refs:uint8_t (Results 1 – 25 of 1557) sorted by relevance
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151 uint8_t link_rate_set;157 uint8_t level : 4;158 uint8_t reserved : 1;159 uint8_t no_preshoot : 1;160 uint8_t no_deemphasis : 1;161 uint8_t method2 : 1;163 uint8_t raw;193 uint8_t VC_PAYLOAD_TABLE_UPDATED:1;194 uint8_t ACT_HANDLED:1;196 uint8_t raw;[all …]
52 #ifndef uint8_t 53 typedef unsigned char uint8_t; typedef234 …uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compa…235 …uint8_t content_revision; //change it when a data table has a structure change, or a hw function…244 …uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to d…447 uint8_t h_border;448 uint8_t v_border;450 uint8_t atom_mode_id;451 uint8_t refreshrate;490 uint8_t mem_module_id; [all …]
158 uint8_t cmd;159 uint8_t cmdid;163 uint8_t logdrv;164 uint8_t numsge;165 uint8_t resvd;166 uint8_t busy;167 uint8_t numstatus;168 uint8_t status;169 uint8_t completed[MBOX_MAX_FIRMWARE_STATUS];170 uint8_t poll;[all …]
46 uint8_t DisplayPhy1Config;47 uint8_t DisplayPhy2Config;48 uint8_t DisplayPhy3Config;49 uint8_t DisplayPhy4Config;51 uint8_t DisplayPhy5Config;52 uint8_t DisplayPhy6Config;53 uint8_t DisplayPhy7Config;54 uint8_t DisplayPhy8Config;60 uint8_t SClkDpmEnabledLevels;61 uint8_t MClkDpmEnabledLevels;[all …]
44 uint8_t vco_setting;45 uint8_t postdiv;55 uint8_t Smio;56 uint8_t padding;72 uint8_t PllRange;73 uint8_t SSc_En;85 uint8_t pcieDpmLevel;86 uint8_t DeepSleepDivId;92 uint8_t SclkDid;93 uint8_t padding;[all …]
33 uint8_t Smio;34 uint8_t padding;51 uint8_t pcieDpmLevel;52 uint8_t DeepSleepDivId;60 uint8_t SclkDid;61 uint8_t DisplayWatermark;62 uint8_t EnabledForActivity;63 uint8_t EnabledForThrottle;64 uint8_t UpHyst;65 uint8_t DownHyst;[all …]
41 uint8_t Smio;42 uint8_t padding;54 uint8_t pcieDpmLevel;55 uint8_t DeepSleepDivId;64 uint8_t SclkDid;65 uint8_t DisplayWatermark;66 uint8_t EnabledForActivity;67 uint8_t EnabledForThrottle;68 uint8_t UpHyst;69 uint8_t DownHyst;[all …]
55 uint8_t DisplayPhy1Config;56 uint8_t DisplayPhy2Config;57 uint8_t DisplayPhy3Config;58 uint8_t DisplayPhy4Config;60 uint8_t DisplayPhy5Config;61 uint8_t DisplayPhy6Config;62 uint8_t DisplayPhy7Config;63 uint8_t DisplayPhy8Config;69 uint8_t SClkDpmEnabledLevels;70 uint8_t MClkDpmEnabledLevels;[all …]
43 uint8_t vco_setting; /* 1: 3-6GHz, 3: 2-4GHz */44 uint8_t postdiv; /* divide by 2^n */53 uint8_t Smio;54 uint8_t padding;70 uint8_t PllRange;71 uint8_t SSc_En;84 uint8_t pcieDpmLevel;85 uint8_t DeepSleepDivId;93 uint8_t SclkDid;94 uint8_t padding;[all …]
35 uint8_t Smio;36 uint8_t padding;52 uint8_t pcieDpmLevel;53 uint8_t DeepSleepDivId;62 uint8_t SclkDid;63 uint8_t DisplayWatermark;64 uint8_t EnabledForActivity;65 uint8_t EnabledForThrottle;66 uint8_t UpHyst;67 uint8_t DownHyst;[all …]
84 uint8_t SsOn;85 uint8_t Did; /* DID */93 uint8_t a0_shift;94 uint8_t a1_shift;95 uint8_t a2_shift;96 uint8_t padding;104 uint8_t m1_shift;105 uint8_t m2_shift;106 uint8_t b_shift;107 uint8_t padding;[all …]
150 uint8_t TdpClampMode;151 uint8_t TdcClampMode;152 uint8_t ThermClampMode;153 uint8_t VoltageBusy;157 uint8_t LevelChangeInProgress;158 uint8_t UpHyst;160 uint8_t DownHyst;161 uint8_t VoltageDownHyst;162 uint8_t DpmEnable;163 uint8_t DpmRunning;[all …]
99 uint8_t flags; /* (1) Status flags. */100 uint8_t dir; /* direction of transfer */335 uint8_t id0; /* 0 */336 uint8_t id1; /* 1 */337 uint8_t id2; /* 2 */338 uint8_t id3; /* 3 */339 uint8_t version; /* 4 */342 uint8_t bios_configuration_mode:2;343 uint8_t bios_disable:1;344 uint8_t selectable_scsi_boot_enable:1;[all …]
409 uint8_t op_code;410 uint8_t command_id;411 uint8_t log_drv;412 uint8_t sg_count;416 uint8_t segment_4G;417 uint8_t enhanced_sg;423 uint8_t op_code;424 uint8_t command_id;434 uint8_t op_code;435 uint8_t command_id;[all …]
77 uint8_t opcode;78 uint8_t flags; /* Final bit */79 uint8_t rsvd2[2];80 uint8_t hlength; /* AHSs total length */81 uint8_t dlength[3]; /* Data length */88 uint8_t other[12];129 uint8_t ahstype;130 uint8_t ahspec[5];139 uint8_t opcode;140 uint8_t flags;[all …]
20 uint8_t entry_type; /* Entry type. */21 uint8_t entry_count; /* Entry count. */22 uint8_t sys_define; /* System defined. */23 uint8_t entry_status; /* Entry Status. */26 uint8_t reserved_0;27 uint8_t port_path_ctrl;34 uint8_t scsi_rsp_dsd_len;35 uint8_t reserved_2;39 uint8_t cntrl_flags;41 uint8_t task_mgmt_flags; /* Task management flags. */[all …]
53 uint8_t current_login_state;54 uint8_t last_login_state;64 uint8_t hard_address[3];65 uint8_t reserved_1;67 uint8_t port_id[3];68 uint8_t sequence_id;77 uint8_t prli_svc_param_word_0[2]; /* Big endian */79 uint8_t prli_svc_param_word_3[2]; /* Big endian */82 uint8_t port_name[WWN_SIZE];83 uint8_t node_name[WWN_SIZE];[all …]
28 uint8_t extra_control_flags;33 uint8_t version;34 uint8_t pad[2];35 uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];46 uint8_t version;47 uint8_t pad[VND_CMD_PAD_SIZE];48 uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];53 uint8_t version;54 uint8_t pad[VND_CMD_PAD_SIZE];55 uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];[all …]
47 uint8_t psi0_enable;48 uint8_t psi1_enable;49 uint8_t max_vid_step;50 uint8_t telemetry_offset;51 uint8_t telemetry_slope;57 uint8_t uc_gpio_pin_bit_shift;66 uint8_t ucPll_ss_enable;67 uint8_t ucReserve;96 uint8_t ucEnableGbVdroopTableCkson;97 uint8_t ucEnableGbFuseTableCkson;[all …]
343 uint8_t Enabled;344 uint8_t Speed;345 uint8_t SlaveAddress; 346 uint8_t ControllerPort;347 uint8_t ControllerName;348 uint8_t ThermalThrotter;349 uint8_t I2cProtocol;350 uint8_t PaddingConfig; 388 uint8_t ReadWriteData; //Return data for read. Data to send for write389 …uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, an…[all …]
42 uint8_t bksv_read;43 uint8_t bksv_validation;44 uint8_t create_session;45 uint8_t an_write;46 uint8_t aksv_write;47 uint8_t ainfo_write;48 uint8_t bcaps_read;49 uint8_t r0p_read;50 uint8_t rx_validation;51 uint8_t encryption;[all …]
243 uint8_t psr;244 uint8_t fw_assisted_mclk_switch;245 uint8_t reserved[6];293 uint8_t dal_fw; /**< 1 if the firmware is DAL */294 uint8_t reserved[3]; /**< padding bits */302 uint8_t reserved[64]; /**< padding bits */885 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];918 uint8_t hubp_inst : 4; /**< HUBP instance */919 uint8_t tmz_surface : 1; /**< TMZ enable or disable */920 uint8_t immediate :1; /**< Immediate flip */[all …]
84 uint8_t hbm_cmd;85 uint8_t data[];98 uint8_t hbm_cmd;99 uint8_t fw_addr;100 uint8_t host_addr;101 uint8_t data;105 uint8_t minor_version;106 uint8_t major_version;110 uint8_t hbm_cmd;111 uint8_t reserved;[all …]