Lines Matching refs:uint8_t
55 uint8_t DisplayPhy1Config;
56 uint8_t DisplayPhy2Config;
57 uint8_t DisplayPhy3Config;
58 uint8_t DisplayPhy4Config;
60 uint8_t DisplayPhy5Config;
61 uint8_t DisplayPhy6Config;
62 uint8_t DisplayPhy7Config;
63 uint8_t DisplayPhy8Config;
69 uint8_t SClkDpmEnabledLevels;
70 uint8_t MClkDpmEnabledLevels;
71 uint8_t LClkDpmEnabledLevels;
72 uint8_t PCIeDpmEnabledLevels;
74 uint8_t UVDDpmEnabledLevels;
75 uint8_t SAMUDpmEnabledLevels;
76 uint8_t ACPDpmEnabledLevels;
77 uint8_t VCEDpmEnabledLevels;
97 uint8_t Smio;
98 uint8_t padding;
111 uint8_t padding1[2];
120 uint8_t SclkDid;
121 uint8_t DisplayWatermark;
122 uint8_t EnabledForActivity;
123 uint8_t EnabledForThrottle;
124 uint8_t UpH;
125 uint8_t DownH;
126 uint8_t VoltageDownH;
127 uint8_t PowerThrottle;
128 uint8_t DeepSleepDivId;
129 uint8_t padding[3];
140 uint8_t SclkDid;
141 uint8_t DisplayWatermark;
142 uint8_t DeepSleepDivId;
143 uint8_t padding;
161 uint8_t VddcOffsetVid;
162 uint8_t VddcPhase;
177 uint8_t EdcReadEnable;
178 uint8_t EdcWriteEnable;
179 uint8_t RttEnable;
180 uint8_t StutterEnable;
182 uint8_t StrobeEnable;
183 uint8_t StrobeRatio;
184 uint8_t EnabledForThrottle;
185 uint8_t EnabledForActivity;
187 uint8_t UpH;
188 uint8_t DownH;
189 uint8_t VoltageDownH;
190 uint8_t padding;
193 uint8_t DisplayWatermark;
194 uint8_t padding1;
211 uint8_t PcieGenSpeed;
212 uint8_t PcieLaneCount;
213 uint8_t EnabledForActivity;
214 uint8_t Padding;
227 uint8_t McArbBurstTime;
228 uint8_t padding[3];
245 uint8_t MinVddcPhases;
246 uint8_t VclkDivider;
247 uint8_t DclkDivider;
248 uint8_t padding[3];
257 uint8_t MinPhases;
258 uint8_t Divider;
274 uint8_t DisplayWatermark;
275 uint8_t McArbIndex;
276 uint8_t McRegIndex;
277 uint8_t SeqIndex;
278 uint8_t SclkDid;
281 uint8_t PCIeGen;
311 uint8_t GraphicsDpmLevelCount;
312 uint8_t MemoryDpmLevelCount;
313 uint8_t LinkLevelCount;
314 uint8_t UvdLevelCount;
315 uint8_t VceLevelCount;
316 uint8_t AcpLevelCount;
317 uint8_t SamuLevelCount;
318 uint8_t MasterDeepSleepControl;
336 uint8_t UvdBootLevel;
337 uint8_t VceBootLevel;
338 uint8_t AcpBootLevel;
339 uint8_t SamuBootLevel;
341 uint8_t UVDInterval;
342 uint8_t VCEInterval;
343 uint8_t ACPInterval;
344 uint8_t SAMUInterval;
346 uint8_t GraphicsBootLevel;
347 uint8_t GraphicsVoltageChangeEnable;
348 uint8_t GraphicsThermThrottleEnable;
349 uint8_t GraphicsInterval;
351 uint8_t VoltageInterval;
352 uint8_t ThermalInterval;
356 uint8_t MemoryBootLevel;
357 uint8_t MemoryVoltageChangeEnable;
359 uint8_t MemoryInterval;
360 uint8_t MemoryThermThrottleEnable;
366 uint8_t PCIeBootLinkLevel;
367 uint8_t PCIeGenInterval;
368 uint8_t DTEInterval;
369 uint8_t DTEMode;
371 uint8_t SVI2Enable;
372 uint8_t VRHotGpio;
373 uint8_t AcDcGpio;
374 uint8_t ThermGpio;
388 uint8_t DTEAmbientTempBase;
389 uint8_t DTETjOffset;
390 uint8_t GpuTjMax;
391 uint8_t GpuTjHyst;
426 uint8_t last;
427 uint8_t reserved[3];
452 uint8_t TempSrc;
461 uint8_t BapmVddCVidHiSidd[8];
464 uint8_t BapmVddCVidLoSidd[8];
467 uint8_t VddCVid[8];
470 uint8_t SviLoadLineEn;
471 uint8_t SviLoadLineVddC;
472 uint8_t SviLoadLineTrimVddC;
473 uint8_t SviLoadLineOffsetVddC;
477 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
478 uint8_t TDC_MAWt;
481 uint8_t TdcWaterfallCtl;
482 uint8_t LPMLTemperatureMin;
483 uint8_t LPMLTemperatureMax;
484 uint8_t Reserved;
487 uint8_t BapmVddCVidHiSidd2[8];
496 uint8_t GnbLPML[16];
499 uint8_t GnbLPMLMaxVid;
500 uint8_t GnbLPMLMinVid;
501 uint8_t Reserved1[2];