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Searched refs:tc_port (Results 1 – 10 of 10) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/i915/display/
Dintel_tc_phy_regs.h11 #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \ argument
12 _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
18 #define MG_TX1_LINK_PARAMS(ln, tc_port) \ argument
19 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
27 #define MG_TX2_LINK_PARAMS(ln, tc_port) \ argument
28 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
37 #define MG_TX1_PISO_READLOAD(ln, tc_port) \ argument
38 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
46 #define MG_TX2_PISO_READLOAD(ln, tc_port) \ argument
47 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
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Dintel_dkl_phy.c16 enum tc_port tc_port = DKL_REG_TC_PORT(reg); in dkl_phy_set_hip_idx() local
18 drm_WARN_ON(&i915->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS); in dkl_phy_set_hip_idx()
21 HIP_INDEX_REG(tc_port), in dkl_phy_set_hip_idx()
22 HIP_INDEX_VAL(tc_port, idx)); in dkl_phy_set_hip_idx()
Dintel_tc.c281 enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); in adl_tc_port_live_status_mask() local
291 val = intel_uncore_read(uncore, TCSS_DDI_STATUS(tc_port)); in adl_tc_port_live_status_mask()
353 enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); in adl_tc_phy_status_complete() local
357 val = intel_uncore_read(uncore, TCSS_DDI_STATUS(tc_port)); in adl_tc_phy_status_complete()
893 enum tc_port tc_port = intel_port_to_tc(i915, port); in tc_port_load_fia_params() local
900 dig_port->tc_phy_fia = tc_port / 2; in tc_port_load_fia_params()
901 dig_port->tc_phy_fia_idx = tc_port % 2; in tc_port_load_fia_params()
904 dig_port->tc_phy_fia_idx = tc_port; in tc_port_load_fia_params()
912 enum tc_port tc_port = intel_port_to_tc(i915, port); in intel_tc_port_init() local
914 if (drm_WARN_ON(&i915->drm, tc_port == TC_PORT_NONE)) in intel_tc_port_init()
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Dintel_dpll_mgr.c197 static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id) in icl_pll_id_to_tc_port()
202 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port) in icl_tc_port_to_pll_id() argument
204 return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1; in icl_tc_port_to_pll_id()
224 enum tc_port tc_port = icl_pll_id_to_tc_port(id); in intel_tc_pll_enable_reg() local
227 return ADLP_PORTTC_PLL_ENABLE(tc_port); in intel_tc_pll_enable_reg()
229 return MG_PLL_ENABLE(tc_port); in intel_tc_pll_enable_reg()
3428 enum tc_port tc_port = icl_pll_id_to_tc_port(id); in mg_pll_get_hw_state() local
3445 MG_REFCLKIN_CTL(tc_port)); in mg_pll_get_hw_state()
3449 intel_de_read(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port)); in mg_pll_get_hw_state()
3454 intel_de_read(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port)); in mg_pll_get_hw_state()
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Dintel_ddi.c1151 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); in icl_mg_phy_set_signal_levels() local
1163 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), in icl_mg_phy_set_signal_levels()
1165 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), in icl_mg_phy_set_signal_levels()
1175 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), in icl_mg_phy_set_signal_levels()
1181 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), in icl_mg_phy_set_signal_levels()
1192 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), in icl_mg_phy_set_signal_levels()
1201 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), in icl_mg_phy_set_signal_levels()
1217 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), in icl_mg_phy_set_signal_levels()
1224 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), in icl_mg_phy_set_signal_levels()
1231 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), in icl_mg_phy_set_signal_levels()
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Dintel_dpll_mgr.h39 enum tc_port;
368 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
Dintel_display.h262 enum tc_port { enum
599 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
Dintel_display_power_well.c530 enum tc_port tc_port; in icl_tc_phy_aux_power_well_enable() local
532 tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); in icl_tc_phy_aux_power_well_enable()
534 if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port), 2) & in icl_tc_phy_aux_power_well_enable()
Dintel_display.c2152 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) in intel_port_to_tc()
/linux-6.1.9/drivers/gpu/drm/i915/
Di915_reg.h7227 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ argument
7228 (tc_port) + 12 : \
7229 (tc_port) - TC_PORT_4 + 21))
7302 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ argument
7313 #define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \ argument
7429 #define DKL_PCS_DW5(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ argument
7450 #define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ argument
7459 #define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ argument
7471 #define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ argument
7480 #define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ argument
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