197 static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)  in icl_pll_id_to_tc_port()
202 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)  in icl_tc_port_to_pll_id()  argument
204 	return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1;  in icl_tc_port_to_pll_id()
224 	enum tc_port tc_port = icl_pll_id_to_tc_port(id);  in intel_tc_pll_enable_reg()  local
227 		return ADLP_PORTTC_PLL_ENABLE(tc_port);  in intel_tc_pll_enable_reg()
229 	return MG_PLL_ENABLE(tc_port);  in intel_tc_pll_enable_reg()
3428 	enum tc_port tc_port = icl_pll_id_to_tc_port(id);  in mg_pll_get_hw_state()  local
3445 						  MG_REFCLKIN_CTL(tc_port));  in mg_pll_get_hw_state()
3449 		intel_de_read(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port));  in mg_pll_get_hw_state()
3454 		intel_de_read(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port));  in mg_pll_get_hw_state()
3461 	hw_state->mg_pll_div0 = intel_de_read(dev_priv, MG_PLL_DIV0(tc_port));  in mg_pll_get_hw_state()
3462 	hw_state->mg_pll_div1 = intel_de_read(dev_priv, MG_PLL_DIV1(tc_port));  in mg_pll_get_hw_state()
3463 	hw_state->mg_pll_lf = intel_de_read(dev_priv, MG_PLL_LF(tc_port));  in mg_pll_get_hw_state()
3465 						   MG_PLL_FRAC_LOCK(tc_port));  in mg_pll_get_hw_state()
3466 	hw_state->mg_pll_ssc = intel_de_read(dev_priv, MG_PLL_SSC(tc_port));  in mg_pll_get_hw_state()
3468 	hw_state->mg_pll_bias = intel_de_read(dev_priv, MG_PLL_BIAS(tc_port));  in mg_pll_get_hw_state()
3470 		intel_de_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port));  in mg_pll_get_hw_state()
3494 	enum tc_port tc_port = icl_pll_id_to_tc_port(id);  in dkl_pll_get_hw_state()  local
3513 						       DKL_REFCLKIN_CTL(tc_port), 2);  in dkl_pll_get_hw_state()
3517 		intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), 2);  in dkl_pll_get_hw_state()
3525 		intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), 2);  in dkl_pll_get_hw_state()
3529 	hw_state->mg_pll_div0 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV0(tc_port), 2);  in dkl_pll_get_hw_state()
3535 	hw_state->mg_pll_div1 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port), 2);  in dkl_pll_get_hw_state()
3539 	hw_state->mg_pll_ssc = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port), 2);  in dkl_pll_get_hw_state()
3545 	hw_state->mg_pll_bias = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port), 2);  in dkl_pll_get_hw_state()
3550 		intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2);  in dkl_pll_get_hw_state()
3680 	enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);  in icl_mg_pll_write()  local
3689 	val = intel_de_read(dev_priv, MG_REFCLKIN_CTL(tc_port));  in icl_mg_pll_write()
3692 	intel_de_write(dev_priv, MG_REFCLKIN_CTL(tc_port), val);  in icl_mg_pll_write()
3694 	val = intel_de_read(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port));  in icl_mg_pll_write()
3697 	intel_de_write(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port), val);  in icl_mg_pll_write()
3699 	val = intel_de_read(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port));  in icl_mg_pll_write()
3705 	intel_de_write(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port), val);  in icl_mg_pll_write()
3707 	intel_de_write(dev_priv, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);  in icl_mg_pll_write()
3708 	intel_de_write(dev_priv, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);  in icl_mg_pll_write()
3709 	intel_de_write(dev_priv, MG_PLL_LF(tc_port), hw_state->mg_pll_lf);  in icl_mg_pll_write()
3710 	intel_de_write(dev_priv, MG_PLL_FRAC_LOCK(tc_port),  in icl_mg_pll_write()
3712 	intel_de_write(dev_priv, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);  in icl_mg_pll_write()
3714 	val = intel_de_read(dev_priv, MG_PLL_BIAS(tc_port));  in icl_mg_pll_write()
3717 	intel_de_write(dev_priv, MG_PLL_BIAS(tc_port), val);  in icl_mg_pll_write()
3719 	val = intel_de_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port));  in icl_mg_pll_write()
3722 	intel_de_write(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port), val);  in icl_mg_pll_write()
3724 	intel_de_posting_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port));  in icl_mg_pll_write()
3731 	enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);  in dkl_pll_write()  local
3739 	val = intel_dkl_phy_read(dev_priv, DKL_REFCLKIN_CTL(tc_port), 2);  in dkl_pll_write()
3742 	intel_dkl_phy_write(dev_priv, DKL_REFCLKIN_CTL(tc_port), 2, val);  in dkl_pll_write()
3744 	val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), 2);  in dkl_pll_write()
3747 	intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), 2, val);  in dkl_pll_write()
3749 	val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), 2);  in dkl_pll_write()
3755 	intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), 2, val);  in dkl_pll_write()
3760 	intel_dkl_phy_rmw(dev_priv, DKL_PLL_DIV0(tc_port), 2, val,  in dkl_pll_write()
3763 	val = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port), 2);  in dkl_pll_write()
3767 	intel_dkl_phy_write(dev_priv, DKL_PLL_DIV1(tc_port), 2, val);  in dkl_pll_write()
3769 	val = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port), 2);  in dkl_pll_write()
3775 	intel_dkl_phy_write(dev_priv, DKL_PLL_SSC(tc_port), 2, val);  in dkl_pll_write()
3777 	val = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port), 2);  in dkl_pll_write()
3781 	intel_dkl_phy_write(dev_priv, DKL_PLL_BIAS(tc_port), 2, val);  in dkl_pll_write()
3783 	val = intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2);  in dkl_pll_write()
3787 	intel_dkl_phy_write(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2, val);  in dkl_pll_write()
3789 	intel_dkl_phy_posting_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2);  in dkl_pll_write()