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Searched refs:ref_div (Results 1 – 25 of 39) sorted by relevance

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/linux-6.1.9/arch/mips/ath79/
Dclock.c148 u32 ref_div; in ar933x_clocks_init() local
167 ref_div = 1; in ar933x_clocks_init()
182 ref_div = t; in ar933x_clocks_init()
205 ref_div * out_div * cpu_div); in ar933x_clocks_init()
207 ref_div * out_div * ddr_div); in ar933x_clocks_init()
209 ref_div * out_div * ahb_div); in ar933x_clocks_init()
212 static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, in ar934x_get_pll_freq() argument
220 do_div(t, ref_div); in ar934x_get_pll_freq()
225 do_div(t, ref_div * frac); in ar934x_get_pll_freq()
238 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; in ar934x_clocks_init() local
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/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Damdgpu_pll.c87 unsigned int *fb_div, unsigned int *ref_div) in amdgpu_pll_get_fb_ref_div() argument
97 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); in amdgpu_pll_get_fb_ref_div()
98 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in amdgpu_pll_get_fb_ref_div()
102 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); in amdgpu_pll_get_fb_ref_div()
136 unsigned ref_div_min, ref_div_max, ref_div; in amdgpu_pll_compute() local
211 ref_div_max, &fb_div, &ref_div); in amdgpu_pll_compute()
213 (ref_div * post_div)); in amdgpu_pll_compute()
226 &fb_div, &ref_div); in amdgpu_pll_compute()
230 amdgpu_pll_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); in amdgpu_pll_compute()
238 ref_div *= tmp; in amdgpu_pll_compute()
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Datombios_crtc.c582 u32 ref_div, in amdgpu_atombios_crtc_program_pll() argument
609 args.v1.usRefDiv = cpu_to_le16(ref_div); in amdgpu_atombios_crtc_program_pll()
619 args.v2.usRefDiv = cpu_to_le16(ref_div); in amdgpu_atombios_crtc_program_pll()
629 args.v3.usRefDiv = cpu_to_le16(ref_div); in amdgpu_atombios_crtc_program_pll()
646 args.v5.ucRefDiv = ref_div; in amdgpu_atombios_crtc_program_pll()
676 args.v6.ucRefDiv = ref_div; in amdgpu_atombios_crtc_program_pll()
826 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in amdgpu_atombios_crtc_set_pll() local
855 &fb_div, &frac_fb_div, &ref_div, &post_div); in amdgpu_atombios_crtc_set_pll()
862 ref_div, fb_div, frac_fb_div, post_div, in amdgpu_atombios_crtc_set_pll()
875 step_size = (4 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) / in amdgpu_atombios_crtc_set_pll()
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Datombios_crtc.h48 u32 ref_div,
Damdgpu_atombios.h43 u32 ref_div; member
/linux-6.1.9/drivers/clk/microchip/
Dclk-mpfs.c102 u32 mult, ref_div, postdiv; in mpfs_clk_msspll_recalc_rate() local
106 ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; in mpfs_clk_msspll_recalc_rate()
107 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); in mpfs_clk_msspll_recalc_rate()
111 return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); in mpfs_clk_msspll_recalc_rate()
119 u32 mult, ref_div; in mpfs_clk_msspll_round_rate() local
124 ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; in mpfs_clk_msspll_round_rate()
125 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); in mpfs_clk_msspll_round_rate()
127 rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; in mpfs_clk_msspll_round_rate()
139 u32 mult, ref_div, postdiv; in mpfs_clk_msspll_set_rate() local
145 ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; in mpfs_clk_msspll_set_rate()
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Dclk-mpfs-ccc.c78 u32 mult, ref_div; in mpfs_ccc_pll_recalc_rate() local
82 ref_div = readl_relaxed(ref_div_addr) >> MPFS_CCC_REFDIV_SHIFT; in mpfs_ccc_pll_recalc_rate()
83 ref_div &= clk_div_mask(MPFS_CCC_REFDIV_WIDTH); in mpfs_ccc_pll_recalc_rate()
85 return prate * mult / (ref_div * MPFS_CCC_FIXED_DIV); in mpfs_ccc_pll_recalc_rate()
/linux-6.1.9/drivers/gpu/drm/radeon/
Dradeon_clocks.c43 uint32_t fb_div, ref_div, post_div, sclk; in radeon_legacy_get_engine_clock() local
50 ref_div = in radeon_legacy_get_engine_clock()
53 if (ref_div == 0) in radeon_legacy_get_engine_clock()
56 sclk = fb_div / ref_div; in radeon_legacy_get_engine_clock()
73 uint32_t fb_div, ref_div, post_div, mclk; in radeon_legacy_get_memory_clock() local
80 ref_div = in radeon_legacy_get_memory_clock()
83 if (ref_div == 0) in radeon_legacy_get_memory_clock()
86 mclk = fb_div / ref_div; in radeon_legacy_get_memory_clock()
356 int ref_div = spll->reference_div; in calc_eng_mem_clock() local
358 if (!ref_div) in calc_eng_mem_clock()
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Dradeon_display.c927 unsigned *fb_div, unsigned *ref_div) in avivo_get_fb_ref_div() argument
933 *ref_div = min(max(den/post_div, 1u), ref_div_max); in avivo_get_fb_ref_div()
934 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in avivo_get_fb_ref_div()
938 *ref_div = (*ref_div * fb_div_max)/(*fb_div); in avivo_get_fb_ref_div()
970 unsigned ref_div_min, ref_div_max, ref_div; in radeon_compute_pll_avivo() local
1048 ref_div_max, &fb_div, &ref_div); in radeon_compute_pll_avivo()
1050 (ref_div * post_div)); in radeon_compute_pll_avivo()
1063 &fb_div, &ref_div); in radeon_compute_pll_avivo()
1067 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); in radeon_compute_pll_avivo()
1075 ref_div *= tmp; in radeon_compute_pll_avivo()
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Drv740_dpm.c140 reference_divider = 1 + dividers.ref_div; in rv740_populate_sclk_value()
147 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv740_populate_sclk_value()
215 mpll_ad_func_cntl |= CLKR(dividers.ref_div); in rv740_populate_mclk_value()
232 mpll_dq_func_cntl |= CLKR(dividers.ref_div); in rv740_populate_mclk_value()
251 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div); in rv740_populate_mclk_value()
Drs780_dpm.c87 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div); in rs780_initialize_dpm_power_state()
453 if ((min_dividers.ref_div != max_dividers.ref_div) || in rs780_set_engine_clock_scaling()
455 (max_dividers.ref_div != current_max_dividers.ref_div) || in rs780_set_engine_clock_scaling()
988 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; in rs780_dpm_debugfs_print_current_performance_level() local
992 (post_div * ref_div); in rs780_dpm_debugfs_print_current_performance_level()
1010 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; in rs780_dpm_get_current_sclk() local
1014 (post_div * ref_div); in rs780_dpm_get_current_sclk()
Datombios_crtc.c822 u32 ref_div, in atombios_crtc_program_pll() argument
849 args.v1.usRefDiv = cpu_to_le16(ref_div); in atombios_crtc_program_pll()
859 args.v2.usRefDiv = cpu_to_le16(ref_div); in atombios_crtc_program_pll()
869 args.v3.usRefDiv = cpu_to_le16(ref_div); in atombios_crtc_program_pll()
886 args.v5.ucRefDiv = ref_div; in atombios_crtc_program_pll()
915 args.v6.ucRefDiv = ref_div; in atombios_crtc_program_pll()
1063 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in atombios_crtc_set_pll() local
1095 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
1098 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
1101 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
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Drv730_dpm.c59 reference_divider = 1 + dividers.ref_div; in rv730_populate_sclk_value()
77 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv730_populate_sclk_value()
137 reference_divider = dividers.ref_div + 1; in rv730_populate_mclk_value()
152 mpll_func_cntl |= MPLL_REF_DIV(dividers.ref_div); in rv730_populate_mclk_value()
Drv770_dpm.c335 reference_divider = dividers->ref_div; in rv770_calculate_fractional_mpll_feedback_divider()
416 if ((dividers.ref_div < 1) || (dividers.ref_div > 5)) in rv770_populate_mclk_value()
434 mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]); in rv770_populate_mclk_value()
462 mpll_dq_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]); in rv770_populate_mclk_value()
512 reference_divider = 1 + dividers.ref_div; in rv770_populate_sclk_value()
528 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv770_populate_sclk_value()
812 (MPLL_LOCK_TIME(R600_MPLLLOCKTIME_DFLT * pi->ref_div) | in rv770_program_mpll_timing_parameters()
2378 pi->ref_div = dividers.ref_div + 1; in rv770_dpm_init()
2380 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; in rv770_dpm_init()
Drv6xx_dpm.c530 (dividers->ref_div + 1); in rv6xx_calculate_vco_frequency()
567 (ref_clk / (dividers.ref_div + 1)), in rv6xx_program_engine_spread_spectrum()
573 (ref_clk / (dividers.ref_div + 1))); in rv6xx_program_engine_spread_spectrum()
606 rv6xx_memory_clock_entry_set_reference_divider(rdev, entry, dividers.ref_div); in rv6xx_program_mclk_stepping_entry()
685 (ref_clk / (dividers.ref_div + 1)), in rv6xx_program_mclk_spread_spectrum_parameters()
691 (ref_clk / (dividers.ref_div + 1))); in rv6xx_program_mclk_spread_spectrum_parameters()
1960 pi->spll_ref_div = dividers.ref_div + 1; in rv6xx_dpm_init()
1967 pi->mpll_ref_div = dividers.ref_div + 1; in rv6xx_dpm_init()
Dradeon_legacy_crtc.c267 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, in radeon_compute_pll_gain() argument
272 if (!ref_div) in radeon_compute_pll_gain()
275 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; in radeon_compute_pll_gain()
Dcypress_dpm.c518 mpll_ad_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
535 mpll_dq_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
559 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div); in cypress_populate_mclk_value()
2057 pi->ref_div = dividers.ref_div + 1; in cypress_dpm_init()
2059 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; in cypress_dpm_init()
Drv770_dpm.h115 u32 ref_div; member
/linux-6.1.9/drivers/media/dvb-frontends/
Dtda8261.c72 static const u8 ref_div[] = { 0x00, 0x01, 0x02, 0x05, 0x07 }; variable
109 buf[2] = (0x01 << 7) | ((ref_div[config->step_size] & 0x07) << 1); in tda8261_set_params()
/linux-6.1.9/drivers/net/wireless/ath/ath9k/
Dar9002_phy.c307 int ref_div = 5; in ar9002_hw_compute_pll_control() local
313 ref_div = 10; in ar9002_hw_compute_pll_control()
320 pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV); in ar9002_hw_compute_pll_control()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hubbub.c544 uint32_t ref_div = 0; in hubbub2_get_dchub_ref_freq() local
547 REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div, in hubbub2_get_dchub_ref_freq()
551 if (ref_div == 2) in hubbub2_get_dchub_ref_freq()
/linux-6.1.9/drivers/gpu/drm/bridge/
Dchipone-icn6211.c261 u8 ref_div; in chipone_configure_pll() local
332 ref_div = PLL_REF_DIV_P(best_p >> best_p_pot) | PLL_REF_DIV_S(best_s); in chipone_configure_pll()
334 ref_div |= PLL_REF_DIV_Pe; in chipone_configure_pll()
339 chipone_writeb(icn, PLL_REF_DIV, ref_div); in chipone_configure_pll()
/linux-6.1.9/drivers/video/fbdev/aty/
Dradeon_base.c579 unsigned sclk, mclk, tmp, ref_div; in radeon_probe_pll_params() local
689 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff; in radeon_probe_pll_params()
699 rinfo->pll.ref_div = ref_div; in radeon_probe_pll_params()
768 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; in radeon_get_pllinfo()
791 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10); in radeon_get_pllinfo()
826 rinfo->pll.ref_div, in radeon_get_pllinfo()
1615 rinfo->pll.ref_div, rinfo->pll.ref_clk, in radeon_calc_pll_regs()
1625 rinfo->pll.ref_div, rinfo->pll.ref_clk, in radeon_calc_pll_regs()
1628 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq, in radeon_calc_pll_regs()
1630 regs->ppll_ref_div = rinfo->pll.ref_div; in radeon_calc_pll_regs()
Datyfb.h51 int ref_div; member
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_hubbub.c920 uint32_t ref_div = 0; in hubbub31_get_dchub_ref_freq() local
924 REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div, in hubbub31_get_dchub_ref_freq()
928 if (ref_div == 2) in hubbub31_get_dchub_ref_freq()

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