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Searched refs:ras (Results 1 – 25 of 62) sorted by relevance

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/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Damdgpu_umc.c38 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_do_page_retirement()
39 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_umc_do_page_retirement()
40 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, ras_error_status); in amdgpu_umc_do_page_retirement()
42 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_do_page_retirement()
43 adev->umc.ras->ras_block.hw_ops->query_ras_error_address && in amdgpu_umc_do_page_retirement()
59 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, ras_error_status); in amdgpu_umc_do_page_retirement()
62 if (adev->umc.ras && in amdgpu_umc_do_page_retirement()
63 adev->umc.ras->ecc_info_query_ras_error_count) in amdgpu_umc_do_page_retirement()
64 adev->umc.ras->ecc_info_query_ras_error_count(adev, ras_error_status); in amdgpu_umc_do_page_retirement()
66 if (adev->umc.ras && in amdgpu_umc_do_page_retirement()
[all …]
Dmca_v3_0.c129 mca->mp0.ras = &mca_v3_0_mp0_ras; in mca_v3_0_init()
130 mca->mp1.ras = &mca_v3_0_mp1_ras; in mca_v3_0_init()
131 mca->mpio.ras = &mca_v3_0_mpio_ras; in mca_v3_0_init()
132 amdgpu_ras_register_ras_block(adev, &mca->mp0.ras->ras_block); in mca_v3_0_init()
133 amdgpu_ras_register_ras_block(adev, &mca->mp1.ras->ras_block); in mca_v3_0_init()
134 amdgpu_ras_register_ras_block(adev, &mca->mpio.ras->ras_block); in mca_v3_0_init()
135 mca->mp0.ras_if = &mca->mp0.ras->ras_block.ras_comm; in mca_v3_0_init()
136 mca->mp1.ras_if = &mca->mp1.ras->ras_block.ras_comm; in mca_v3_0_init()
137 mca->mpio.ras_if = &mca->mpio.ras->ras_block.ras_comm; in mca_v3_0_init()
Damdgpu_ras.c937 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in amdgpu_ras_get_ecc_info() local
944 ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc)); in amdgpu_ras_get_ecc_info()
946 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_ras_get_ecc_info()
947 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_ras_get_ecc_info()
948 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data); in amdgpu_ras_get_ecc_info()
953 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_ras_get_ecc_info()
954 adev->umc.ras->ras_block.hw_ops->query_ras_error_address) in amdgpu_ras_get_ecc_info()
955 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data); in amdgpu_ras_get_ecc_info()
957 if (adev->umc.ras && in amdgpu_ras_get_ecc_info()
958 adev->umc.ras->ecc_info_query_ras_error_count) in amdgpu_ras_get_ecc_info()
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Dgmc_v9_0.c1211 adev->umc.ras = &umc_v6_1_ras; in gmc_v9_0_set_umc_funcs()
1219 adev->umc.ras = &umc_v6_1_ras; in gmc_v9_0_set_umc_funcs()
1228 adev->umc.ras = &umc_v6_7_ras; in gmc_v9_0_set_umc_funcs()
1238 if (adev->umc.ras) { in gmc_v9_0_set_umc_funcs()
1239 amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block); in gmc_v9_0_set_umc_funcs()
1241 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc"); in gmc_v9_0_set_umc_funcs()
1242 adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC; in gmc_v9_0_set_umc_funcs()
1243 adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in gmc_v9_0_set_umc_funcs()
1244 adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm; in gmc_v9_0_set_umc_funcs()
1247 if (!adev->umc.ras->ras_block.ras_late_init) in gmc_v9_0_set_umc_funcs()
[all …]
Damdgpu_ras_eeprom.c549 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in amdgpu_ras_eeprom_update_header() local
557 control->ras_num_recs >= ras->bad_page_cnt_threshold) { in amdgpu_ras_eeprom_update_header()
560 control->ras_num_recs, ras->bad_page_cnt_threshold); in amdgpu_ras_eeprom_update_header()
806 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in amdgpu_ras_debugfs_eeprom_size_read() local
807 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; in amdgpu_ras_debugfs_eeprom_size_read()
814 if (!ras || !control) { in amdgpu_ras_debugfs_eeprom_size_read()
863 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, in amdgpu_ras_debugfs_set_ret_size() local
865 struct dentry *de = ras->de_ras_eeprom_table; in amdgpu_ras_debugfs_set_ret_size()
875 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in amdgpu_ras_debugfs_table_read() local
876 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control; in amdgpu_ras_debugfs_table_read()
[all …]
Dumc_v6_7.c108 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_query_correctable_error_count() local
116 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_query_correctable_error_count()
123 if (ras->umc_ecc.record_ce_addr_supported) { in umc_v6_7_ecc_info_query_correctable_error_count()
128 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_ceumc_addr; in umc_v6_7_ecc_info_query_correctable_error_count()
150 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_querry_uncorrectable_error_count() local
157 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
232 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_query_error_address() local
235 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_query_error_address()
247 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v6_7_ecc_info_query_error_address()
Dumc_v8_7.c56 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_query_correctable_error_count() local
63 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_query_correctable_error_count()
75 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_querry_uncorrectable_error_count() local
80 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
137 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_query_error_address() local
140 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_query_error_address()
152 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v8_7_ecc_info_query_error_address()
Dgmc_v11_0.c555 adev->umc.ras = &umc_v8_10_ras; in gmc_v11_0_set_umc_funcs()
563 if (adev->umc.ras) { in gmc_v11_0_set_umc_funcs()
564 amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block); in gmc_v11_0_set_umc_funcs()
566 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc"); in gmc_v11_0_set_umc_funcs()
567 adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC; in gmc_v11_0_set_umc_funcs()
568 adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in gmc_v11_0_set_umc_funcs()
569 adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm; in gmc_v11_0_set_umc_funcs()
572 if (!adev->umc.ras->ras_block.ras_late_init) in gmc_v11_0_set_umc_funcs()
573 adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init; in gmc_v11_0_set_umc_funcs()
576 if (!adev->umc.ras->ras_block.ras_cb) in gmc_v11_0_set_umc_funcs()
[all …]
Djpeg_v2_5.c804 adev->jpeg.ras = &jpeg_v2_6_ras; in jpeg_v2_5_set_ras_funcs()
810 if (adev->jpeg.ras) { in jpeg_v2_5_set_ras_funcs()
811 amdgpu_ras_register_ras_block(adev, &adev->jpeg.ras->ras_block); in jpeg_v2_5_set_ras_funcs()
813 strcpy(adev->jpeg.ras->ras_block.ras_comm.name, "jpeg"); in jpeg_v2_5_set_ras_funcs()
814 adev->jpeg.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG; in jpeg_v2_5_set_ras_funcs()
815 adev->jpeg.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; in jpeg_v2_5_set_ras_funcs()
816 adev->jpeg.ras_if = &adev->jpeg.ras->ras_block.ras_comm; in jpeg_v2_5_set_ras_funcs()
819 if (!adev->jpeg.ras->ras_block.ras_late_init) in jpeg_v2_5_set_ras_funcs()
820 adev->jpeg.ras->ras_block.ras_late_init = amdgpu_ras_block_late_init; in jpeg_v2_5_set_ras_funcs()
Dgmc_v10_0.c681 adev->umc.ras = &umc_v8_7_ras; in gmc_v10_0_set_umc_funcs()
686 if (adev->umc.ras) { in gmc_v10_0_set_umc_funcs()
687 amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block); in gmc_v10_0_set_umc_funcs()
689 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc"); in gmc_v10_0_set_umc_funcs()
690 adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC; in gmc_v10_0_set_umc_funcs()
691 adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in gmc_v10_0_set_umc_funcs()
692 adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm; in gmc_v10_0_set_umc_funcs()
695 if (!adev->umc.ras->ras_block.ras_late_init) in gmc_v10_0_set_umc_funcs()
696 adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init; in gmc_v10_0_set_umc_funcs()
699 if (!adev->umc.ras->ras_block.ras_cb) in gmc_v10_0_set_umc_funcs()
[all …]
Dsoc15.c504 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in soc15_asic_baco_reset() local
508 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
516 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
527 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in soc15_asic_reset_method() local
561 if (ras && adev->ras_enabled && in soc15_asic_reset_method()
1269 if (adev->nbio.ras && in soc15_common_hw_fini()
1270 adev->nbio.ras->init_ras_controller_interrupt) in soc15_common_hw_fini()
1272 if (adev->nbio.ras && in soc15_common_hw_fini()
1273 adev->nbio.ras->init_ras_err_event_athub_interrupt) in soc15_common_hw_fini()
Damdgpu_hdp.h43 struct amdgpu_hdp_ras *ras; member
Damdgpu_mca.h30 struct amdgpu_mca_ras_block *ras; member
Dsdma_v4_0.c1799 if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops && in sdma_v4_0_late_init()
1800 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count) in sdma_v4_0_late_init()
1801 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev); in sdma_v4_0_late_init()
2725 adev->sdma.ras = &sdma_v4_0_ras; in sdma_v4_0_set_ras_funcs()
2728 adev->sdma.ras = &sdma_v4_4_ras; in sdma_v4_0_set_ras_funcs()
2734 if (adev->sdma.ras) { in sdma_v4_0_set_ras_funcs()
2735 amdgpu_ras_register_ras_block(adev, &adev->sdma.ras->ras_block); in sdma_v4_0_set_ras_funcs()
2737 strcpy(adev->sdma.ras->ras_block.ras_comm.name, "sdma"); in sdma_v4_0_set_ras_funcs()
2738 adev->sdma.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__SDMA; in sdma_v4_0_set_ras_funcs()
2739 adev->sdma.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in sdma_v4_0_set_ras_funcs()
[all …]
Damdgpu_mmhub.h48 struct amdgpu_mmhub_ras *ras; member
Damdgpu_jpeg.h58 struct amdgpu_jpeg_ras *ras; member
/linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega20_baco.c77 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in vega20_baco_set_state() local
88 if (!ras || !adev->ras_enabled) { in vega20_baco_set_state()
/linux-6.1.9/drivers/edac/
Di5000_edac.c471 int ras, cas; in i5000_process_fatal_error_info() local
484 ras = NREC_RAS(info->nrecmemb); in i5000_process_fatal_error_info()
489 rdwr ? "Write" : "Read", ras, cas); in i5000_process_fatal_error_info()
525 bank, ras, cas, allErrors, specific); in i5000_process_fatal_error_info()
556 int ras, cas; in i5000_process_nonfatal_error_info() local
579 ras = NREC_RAS(info->nrecmemb); in i5000_process_nonfatal_error_info()
584 rdwr ? "Write" : "Read", ras, cas); in i5000_process_nonfatal_error_info()
624 rank, bank, ras, cas, ue_errors, specific); in i5000_process_nonfatal_error_info()
651 ras = REC_RAS(info->recmemb); in i5000_process_nonfatal_error_info()
656 rdwr ? "Write" : "Read", ras, cas); in i5000_process_nonfatal_error_info()
[all …]
Di5100_edac.c433 unsigned ras, in i5100_handle_ce() argument
441 bank, cas, ras); in i5100_handle_ce()
455 unsigned ras, in i5100_handle_ue() argument
463 bank, cas, ras); in i5100_handle_ue()
483 unsigned ras; in i5100_read_log() local
503 ras = i5100_recmemb_ras(dw2); in i5100_read_log()
512 i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg); in i5100_read_log()
525 ras = i5100_nrecmemb_ras(dw2); in i5100_read_log()
534 i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg); in i5100_read_log()
Di5400_edac.c522 int ras, cas; in i5400_proccess_non_recoverable_info() local
548 ras = nrec_ras(info); in i5400_proccess_non_recoverable_info()
553 buf_id, rdwr_str(rdwr), ras, cas); in i5400_proccess_non_recoverable_info()
561 bank, buf_id, ras, cas, allErrors, error_name[errnum]); in i5400_proccess_non_recoverable_info()
586 int ras, cas; in i5400_process_nonfatal_error_info() local
618 ras = rec_ras(info); in i5400_process_nonfatal_error_info()
626 rdwr_str(rdwr), ras, cas); in i5400_process_nonfatal_error_info()
632 branch >> 1, bank, rdwr_str(rdwr), ras, cas, in i5400_process_nonfatal_error_info()
/linux-6.1.9/net/netfilter/
Dnf_conntrack_h323_main.c1625 unsigned char **data, RasMessage *ras) in process_ras() argument
1627 switch (ras->choice) { in process_ras()
1630 &ras->gatekeeperRequest); in process_ras()
1633 &ras->gatekeeperConfirm); in process_ras()
1636 &ras->registrationRequest); in process_ras()
1639 &ras->registrationConfirm); in process_ras()
1642 &ras->unregistrationRequest); in process_ras()
1645 &ras->admissionRequest); in process_ras()
1648 &ras->admissionConfirm); in process_ras()
1651 &ras->locationRequest); in process_ras()
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/linux-6.1.9/drivers/ras/
DMakefile2 obj-$(CONFIG_RAS) += ras.o
Dras.c14 #define TRACE_INCLUDE_PATH ../../include/ras
/linux-6.1.9/Documentation/gpu/amdgpu/
Dindex.rst14 ras
/linux-6.1.9/include/linux/netfilter/
Dnf_conntrack_h323_asn1.h91 int DecodeRasMessage(unsigned char *buf, size_t sz, RasMessage * ras);

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