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Searched refs:nbio (Results 1 – 25 of 34) sorted by relevance

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/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dnv.c238 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_rreg()
239 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_rreg()
248 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_wreg()
249 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_wreg()
257 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_rreg64()
258 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_rreg64()
267 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_wreg64()
268 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_wreg64()
303 return adev->nbio.funcs->get_memsize(adev); in nv_get_config_memsize()
429 u32 memsize = adev->nbio.funcs->get_memsize(adev); in nv_asic_mode2_reset()
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Dsoc21.c99 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc21_pcie_rreg()
100 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc21_pcie_rreg()
109 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc21_pcie_wreg()
110 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc21_pcie_wreg()
118 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc21_pcie_rreg64()
119 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc21_pcie_rreg64()
128 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc21_pcie_wreg64()
129 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc21_pcie_wreg64()
164 return adev->nbio.funcs->get_memsize(adev); in soc21_get_config_memsize()
297 u32 memsize = adev->nbio.funcs->get_memsize(adev);
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Dsoc15.c200 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_rreg()
201 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_rreg()
210 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_wreg()
211 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_wreg()
219 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_rreg64()
220 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_rreg64()
229 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_wreg64()
230 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_wreg64()
337 return adev->nbio.funcs->get_memsize(adev); in soc15_get_config_memsize()
509 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); in soc15_asic_baco_reset()
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Ddf_v3_6.c51 address = adev->nbio.funcs->get_pcie_index_offset(adev); in df_v3_6_get_fica()
52 data = adev->nbio.funcs->get_pcie_data_offset(adev); in df_v3_6_get_fica()
74 address = adev->nbio.funcs->get_pcie_index_offset(adev); in df_v3_6_set_fica()
75 data = adev->nbio.funcs->get_pcie_data_offset(adev); in df_v3_6_set_fica()
102 address = adev->nbio.funcs->get_pcie_index_offset(adev); in df_v3_6_perfmon_rreg()
103 data = adev->nbio.funcs->get_pcie_data_offset(adev); in df_v3_6_perfmon_rreg()
124 address = adev->nbio.funcs->get_pcie_index_offset(adev); in df_v3_6_perfmon_wreg()
125 data = adev->nbio.funcs->get_pcie_data_offset(adev); in df_v3_6_perfmon_wreg()
143 address = adev->nbio.funcs->get_pcie_index_offset(adev); in df_v3_6_perfmon_arm_with_status()
144 data = adev->nbio.funcs->get_pcie_data_offset(adev); in df_v3_6_perfmon_arm_with_status()
Damdgpu_nbio.c33 r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0); in amdgpu_nbio_ras_late_init()
36 r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); in amdgpu_nbio_ras_late_init()
Dnbio_v7_4.c367 struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if); in nbio_v7_4_handle_ras_controller_intr_no_bifring()
404 get_ras_block_str(adev->nbio.ras_if)); in nbio_v7_4_handle_ras_controller_intr_no_bifring()
410 get_ras_block_str(adev->nbio.ras_if)); in nbio_v7_4_handle_ras_controller_intr_no_bifring()
553 adev->nbio.ras_controller_irq.funcs = in nbio_v7_4_init_ras_controller_interrupt()
555 adev->nbio.ras_controller_irq.num_types = 1; in nbio_v7_4_init_ras_controller_interrupt()
560 &adev->nbio.ras_controller_irq); in nbio_v7_4_init_ras_controller_interrupt()
571 adev->nbio.ras_err_event_athub_irq.funcs = in nbio_v7_4_init_ras_err_event_athub_interrupt()
573 adev->nbio.ras_err_event_athub_irq.num_types = 1; in nbio_v7_4_init_ras_err_event_athub_interrupt()
578 &adev->nbio.ras_err_event_athub_irq); in nbio_v7_4_init_ras_err_event_athub_interrupt()
Damdgpu_ras.c1550 if (adev->nbio.ras && in amdgpu_ras_interrupt_fatal_error_handler()
1551 adev->nbio.ras->handle_ras_controller_intr_no_bifring) in amdgpu_ras_interrupt_fatal_error_handler()
1552 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev); in amdgpu_ras_interrupt_fatal_error_handler()
1554 if (adev->nbio.ras && in amdgpu_ras_interrupt_fatal_error_handler()
1555 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring) in amdgpu_ras_interrupt_fatal_error_handler()
1556 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev); in amdgpu_ras_interrupt_fatal_error_handler()
2458 adev->nbio.ras = &nbio_v7_4_ras; in amdgpu_ras_init()
2459 amdgpu_ras_register_ras_block(adev, &adev->nbio.ras->ras_block); in amdgpu_ras_init()
2460 adev->nbio.ras_if = &adev->nbio.ras->ras_block.ras_comm; in amdgpu_ras_init()
2468 if (adev->nbio.ras && in amdgpu_ras_init()
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Damdgpu_discovery.c2218 adev->nbio.funcs = &nbio_v6_1_funcs; in amdgpu_discovery_set_ip_blocks()
2219 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2224 adev->nbio.funcs = &nbio_v7_0_funcs; in amdgpu_discovery_set_ip_blocks()
2225 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2230 adev->nbio.funcs = &nbio_v7_4_funcs; in amdgpu_discovery_set_ip_blocks()
2231 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2238 adev->nbio.funcs = &nbio_v7_2_funcs; in amdgpu_discovery_set_ip_blocks()
2239 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2249 adev->nbio.funcs = &nbio_v2_3_funcs; in amdgpu_discovery_set_ip_blocks()
2250 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
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Damdgpu_bios.c499 if (adev->nbio.funcs && in amdgpu_soc15_read_bios_from_rom()
500 adev->nbio.funcs->get_rom_offset) { in amdgpu_soc15_read_bios_from_rom()
501 rom_offset = adev->nbio.funcs->get_rom_offset(adev); in amdgpu_soc15_read_bios_from_rom()
Dvega10_ih.c273 adev->nbio.funcs->ih_control(adev); in vega10_ih_irq_init()
293 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, in vega10_ih_irq_init()
Dvega20_ih.c309 adev->nbio.funcs->ih_control(adev); in vega20_ih_irq_init()
344 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, in vega20_ih_irq_init()
Dih_v6_0.c306 adev->nbio.funcs->ih_control(adev); in ih_v6_0_irq_init()
327 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, in ih_v6_0_irq_init()
Dnavi10_ih.c329 adev->nbio.funcs->ih_control(adev); in navi10_ih_irq_init()
361 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, in navi10_ih_irq_init()
Dsdma_v6_0.c333 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; in sdma_v6_0_ring_emit_hdp_flush()
340 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); in sdma_v6_0_ring_emit_hdp_flush()
341 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); in sdma_v6_0_ring_emit_hdp_flush()
555 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, in sdma_v6_0_gfx_resume()
Damdgpu_device.c4664 u32 memsize = adev->nbio.funcs->get_memsize(adev); in amdgpu_device_mode1_reset()
5669 adev->nbio.funcs->enable_doorbell_interrupt) in amdgpu_device_baco_enter()
5670 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); in amdgpu_device_baco_enter()
5689 adev->nbio.funcs->enable_doorbell_interrupt) in amdgpu_device_baco_exit()
5690 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); in amdgpu_device_baco_exit()
5693 adev->nbio.funcs->clear_doorbell_interrupt) in amdgpu_device_baco_exit()
5694 adev->nbio.funcs->clear_doorbell_interrupt(adev); in amdgpu_device_baco_exit()
6006 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); in amdgpu_device_pcie_port_rreg()
6007 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); in amdgpu_device_pcie_port_rreg()
6022 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); in amdgpu_device_pcie_port_wreg()
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Dsdma_v5_2.c346 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; in sdma_v5_2_ring_emit_hdp_flush()
353 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); in sdma_v5_2_ring_emit_hdp_flush()
354 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); in sdma_v5_2_ring_emit_hdp_flush()
619 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, in sdma_v5_2_gfx_resume()
Dsdma_v5_0.c513 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; in sdma_v5_0_ring_emit_hdp_flush()
523 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); in sdma_v5_0_ring_emit_hdp_flush()
524 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); in sdma_v5_0_ring_emit_hdp_flush()
797 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, in sdma_v5_0_gfx_resume()
Djpeg_v3_0.c148 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, in jpeg_v3_0_hw_init()
Djpeg_v4_0.c137 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, in jpeg_v4_0_hw_init()
Djpeg_v2_0.c134 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, in jpeg_v2_0_hw_init()
Djpeg_v2_5.c182 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, in jpeg_v2_5_hw_init()
Dsdma_v4_0.c858 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; in sdma_v4_0_ring_emit_hdp_flush()
863 adev->nbio.funcs->get_hdp_flush_done_offset(adev), in sdma_v4_0_ring_emit_hdp_flush()
864 adev->nbio.funcs->get_hdp_flush_req_offset(adev), in sdma_v4_0_ring_emit_hdp_flush()
Dgmc_v11_0.c677 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; in gmc_v11_0_mc_init()
Dgmc_v10_0.c817 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; in gmc_v10_0_mc_init()
/linux-6.1.9/drivers/block/xen-blkback/
Dblkback.c1195 int i, nbio = 0; in dispatch_rw_block_io() local
1333 biolist[nbio++] = bio; in dispatch_rw_block_io()
1348 biolist[nbio++] = bio; in dispatch_rw_block_io()
1353 atomic_set(&pending_req->pendcnt, nbio); in dispatch_rw_block_io()
1356 for (i = 0; i < nbio; i++) in dispatch_rw_block_io()

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