200 	address = adev->nbio.funcs->get_pcie_index_offset(adev);  in soc15_pcie_rreg()
201 	data = adev->nbio.funcs->get_pcie_data_offset(adev);  in soc15_pcie_rreg()
210 	address = adev->nbio.funcs->get_pcie_index_offset(adev);  in soc15_pcie_wreg()
211 	data = adev->nbio.funcs->get_pcie_data_offset(adev);  in soc15_pcie_wreg()
219 	address = adev->nbio.funcs->get_pcie_index_offset(adev);  in soc15_pcie_rreg64()
220 	data = adev->nbio.funcs->get_pcie_data_offset(adev);  in soc15_pcie_rreg64()
229 	address = adev->nbio.funcs->get_pcie_index_offset(adev);  in soc15_pcie_wreg64()
230 	data = adev->nbio.funcs->get_pcie_data_offset(adev);  in soc15_pcie_wreg64()
337 	return adev->nbio.funcs->get_memsize(adev);  in soc15_get_config_memsize()
509 		adev->nbio.funcs->enable_doorbell_interrupt(adev, false);  in soc15_asic_baco_reset()
517 		adev->nbio.funcs->enable_doorbell_interrupt(adev, true);  in soc15_asic_baco_reset()
677 	    (adev->nbio.funcs->program_aspm))  in soc15_program_aspm()
678 		adev->nbio.funcs->program_aspm(adev);  in soc15_program_aspm()
684 	adev->nbio.funcs->enable_doorbell_aperture(adev, enable);  in soc15_enable_doorbell_aperture()
685 	adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);  in soc15_enable_doorbell_aperture()
699 	return adev->nbio.funcs->get_rev_id(adev);  in soc15_get_rev_id()
1221 			adev->nbio.funcs->sdma_doorbell_range(adev, i,  in soc15_sdma_doorbell_range_init()
1237 	adev->nbio.funcs->init_registers(adev);  in soc15_common_hw_init()
1242 	if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))  in soc15_common_hw_init()
1243 		adev->nbio.funcs->remap_hdp_registers(adev);  in soc15_common_hw_init()
1267 	if (adev->nbio.ras_if &&  in soc15_common_hw_fini()
1268 	    amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {  in soc15_common_hw_fini()
1269 		if (adev->nbio.ras &&  in soc15_common_hw_fini()
1270 		    adev->nbio.ras->init_ras_controller_interrupt)  in soc15_common_hw_fini()
1271 			amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);  in soc15_common_hw_fini()
1272 		if (adev->nbio.ras &&  in soc15_common_hw_fini()
1273 		    adev->nbio.ras->init_ras_err_event_athub_interrupt)  in soc15_common_hw_fini()
1274 			amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);  in soc15_common_hw_fini()
1365 		adev->nbio.funcs->update_medium_grain_clock_gating(adev,  in soc15_common_set_clockgating_state()
1367 		adev->nbio.funcs->update_medium_grain_light_sleep(adev,  in soc15_common_set_clockgating_state()
1383 		adev->nbio.funcs->update_medium_grain_clock_gating(adev,  in soc15_common_set_clockgating_state()
1385 		adev->nbio.funcs->update_medium_grain_light_sleep(adev,  in soc15_common_set_clockgating_state()
1413 	adev->nbio.funcs->get_clockgating_state(adev, flags);  in soc15_common_get_clockgating_state()