Searched refs:mtk_phy_update_field (Results 1 – 8 of 8) sorted by relevance
/linux-6.1.9/drivers/phy/mediatek/ |
D | phy-mtk-hdmi-mt2701.c | 116 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IC_MASK, 0x1); in mtk_hdmi_pll_set_rate() 117 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IR_MASK, 0x1); in mtk_hdmi_pll_set_rate() 118 mtk_phy_update_field(base + HDMI_CON2, RG_HDMITX_TX_POSDIV_MASK, pos_div); in mtk_hdmi_pll_set_rate() 119 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKSEL_MASK, 1); in mtk_hdmi_pll_set_rate() 120 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKDIV_MASK, 19); in mtk_hdmi_pll_set_rate() 121 mtk_phy_update_field(base + HDMI_CON7, RG_HTPLL_DIVEN_MASK, 0x2); in mtk_hdmi_pll_set_rate() 122 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BP_MASK, 0xc); in mtk_hdmi_pll_set_rate() 123 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BC_MASK, 0x2); in mtk_hdmi_pll_set_rate() 124 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BR_MASK, 0x1); in mtk_hdmi_pll_set_rate() 127 mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PRED_IBIAS_MASK, 0x3); in mtk_hdmi_pll_set_rate() [all …]
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D | phy-mtk-tphy.c | 402 mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL, in hs_slew_rate_calibrate() 421 mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG0, P3A_RG_XTAL_EXT_EN_U3, 2); in u3_phy_instance_init() 423 mtk_phy_update_field(phya + U3P_U3_PHYA_REG9, P3A_RG_RX_DAC_MUX, 4); in u3_phy_instance_init() 425 mtk_phy_update_field(phya + U3P_U3_PHYA_REG6, P3A_RG_TX_EIDLE_CM, 0xe); in u3_phy_instance_init() 432 mtk_phy_update_field(phyd + U3P_U3_PHYD_LFPS1, P3D_RG_FWAKE_TH, 0x34); in u3_phy_instance_init() 434 mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET1, P3D_RG_RXDET_STB2_SET, 0x10); in u3_phy_instance_init() 436 mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET2, P3D_RG_RXDET_STB2_SET_P3, 0x10); in u3_phy_instance_init() 450 mtk_phy_update_field(com + U3P_USBPHYACR0, PA0_USB20_PLL_PREDIV, 0); in u2_phy_pll_26m_set() 452 mtk_phy_update_field(com + U3P_USBPHYACR2, PA2_RG_U2PLL_BW, 3); in u2_phy_pll_26m_set() 498 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_SQTH, 2); in u2_phy_instance_init() [all …]
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D | phy-mtk-xsphy.c | 129 mtk_phy_update_field(pbase + XSP_U2FREQ_FMCR0, P2F_RG_CYCLECNT, in u2_phy_slew_rate_calibrate() 161 mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL, calib_val); in u2_phy_slew_rate_calibrate() 274 mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_INTR_CAL, in u2_phy_props_set() 278 mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL, in u2_phy_props_set() 282 mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_VRT_SEL, in u2_phy_props_set() 286 mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_TERM_SEL, in u2_phy_props_set() 296 mtk_phy_update_field(xsphy->glb_base + SSPXTP_PHYA_GLB_00, in u3_phy_props_set() 300 mtk_phy_update_field(pbase + SSPXTP_PHYA_LN_04, in u3_phy_props_set() 304 mtk_phy_update_field(pbase + SSPXTP_PHYA_LN_14, in u3_phy_props_set()
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D | phy-mtk-pcie.c | 92 mtk_phy_update_field(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_PMOS_SEL, in mtk_pcie_efuse_set_lane() 95 mtk_phy_update_field(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_NMOS_SEL, in mtk_pcie_efuse_set_lane() 98 mtk_phy_update_field(addr + PEXTP_ANA_RX_REG, EFUSE_LN_RX_SEL, in mtk_pcie_efuse_set_lane() 119 mtk_phy_update_field(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG, in mtk_pcie_phy_init()
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D | phy-mtk-hdmi-mt8173.c | 160 mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_PLL_PREDIV, pre_div); in mtk_hdmi_pll_set_rate() 166 mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV, div); in mtk_hdmi_pll_set_rate() 171 mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PLL_DIVEN, 0x2); in mtk_hdmi_pll_set_rate() 196 mtk_phy_update_field(base + HDMI_CON3, RG_HDMITX_DRV_IMP_EN, imp_en); in mtk_hdmi_pll_set_rate()
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D | phy-mtk-mipi-dsi-mt8183.c | 83 mtk_phy_update_field(base + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, txdiv0); in mtk_mipi_tx_pll_enable() 149 mtk_phy_update_field(base + MIPITX_VOLTAGE_SEL, RG_DSI_HSTX_LDO_REF_SEL, in mtk_mipi_tx_power_on_signal()
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D | phy-mtk-io.h | 40 #define mtk_phy_update_field(reg, mask, val) \ macro
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D | phy-mtk-mipi-dsi-mt8173.c | 207 mtk_phy_update_field(base + MIPITX_DSI_PLL_TOP, in mtk_mipi_tx_pll_prepare()
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