402 	mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL,  in hs_slew_rate_calibrate()
421 	mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG0, P3A_RG_XTAL_EXT_EN_U3, 2);  in u3_phy_instance_init()
423 	mtk_phy_update_field(phya + U3P_U3_PHYA_REG9, P3A_RG_RX_DAC_MUX, 4);  in u3_phy_instance_init()
425 	mtk_phy_update_field(phya + U3P_U3_PHYA_REG6, P3A_RG_TX_EIDLE_CM, 0xe);  in u3_phy_instance_init()
432 	mtk_phy_update_field(phyd + U3P_U3_PHYD_LFPS1, P3D_RG_FWAKE_TH, 0x34);  in u3_phy_instance_init()
434 	mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET1, P3D_RG_RXDET_STB2_SET, 0x10);  in u3_phy_instance_init()
436 	mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET2, P3D_RG_RXDET_STB2_SET_P3, 0x10);  in u3_phy_instance_init()
450 	mtk_phy_update_field(com + U3P_USBPHYACR0, PA0_USB20_PLL_PREDIV, 0);  in u2_phy_pll_26m_set()
452 	mtk_phy_update_field(com + U3P_USBPHYACR2, PA2_RG_U2PLL_BW, 3);  in u2_phy_pll_26m_set()
498 	mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_SQTH, 2);  in u2_phy_instance_init()
605 	mtk_phy_update_field(phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP, 0x4);  in pcie_phy_instance_init()
607 	mtk_phy_update_field(phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF, 0x1);  in pcie_phy_instance_init()
610 	mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG20, P3A_RG_PLL_DELTA1_PE2H, 0x3c);  in pcie_phy_instance_init()
612 	mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG25, P3A_RG_PLL_DELTA_PE2H, 0x36);  in pcie_phy_instance_init()
624 	mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG6, P3A_RG_PLL_IR_PE2H, 0x2);  in pcie_phy_instance_init()
626 	mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG7, P3A_RG_PLL_BP_PE2H, 0xa);  in pcie_phy_instance_init()
629 	mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET1,  in pcie_phy_instance_init()
632 	mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET2,  in pcie_phy_instance_init()
677 	mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL4, RG_CDR_BIRLTD0_GEN1_MSK, 0x18);  in sata_phy_instance_init()
679 	mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL5, RG_CDR_BIRLTD0_GEN3_MSK, 0x06);  in sata_phy_instance_init()
691 	mtk_phy_update_field(phyd + PHYD_DESIGN_OPTION2, RG_LOCK_CNT_SEL_MSK, 0x02);  in sata_phy_instance_init()
703 	mtk_phy_update_field(phyd + ANA_RG_CTRL_SIGNAL1, RG_IDRV_0DB_GEN1_MSK, 0x20);  in sata_phy_instance_init()
705 	mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL1, RG_EQ_DLEQ_LFI_GEN1_MSK, 0x03);  in sata_phy_instance_init()
801 		mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL,  in u2_phy_props_set()
805 		mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL,  in u2_phy_props_set()
809 		mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL,  in u2_phy_props_set()
817 		mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL,  in u2_phy_props_set()
822 		mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH,  in u2_phy_props_set()
826 		mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP,  in u2_phy_props_set()
976 		mtk_phy_update_field(u2_banks->com + U3P_USBPHYACR1, PA1_RG_INTR_CAL,  in phy_efuse_set()
983 		mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL,  in phy_efuse_set()
987 		mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL,  in phy_efuse_set()
991 		mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_IEXT_INTR,  in phy_efuse_set()