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Searched refs:mdp4_write (Results 1 – 9 of 9) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4_lcdc_encoder.c80 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0), in setup_phy()
85 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(0), in setup_phy()
89 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(1), in setup_phy()
94 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(1), in setup_phy()
98 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(2), in setup_phy()
103 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(2), in setup_phy()
107 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(3), in setup_phy()
112 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(3), in setup_phy()
134 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0), in setup_phy()
139 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(0), in setup_phy()
[all …]
Dmdp4_dsi_encoder.c71 mdp4_write(mdp4_kms, REG_MDP4_DSI_HSYNC_CTRL, in mdp4_dsi_encoder_mode_set()
74 mdp4_write(mdp4_kms, REG_MDP4_DSI_VSYNC_PERIOD, vsync_period); in mdp4_dsi_encoder_mode_set()
75 mdp4_write(mdp4_kms, REG_MDP4_DSI_VSYNC_LEN, vsync_len); in mdp4_dsi_encoder_mode_set()
76 mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_HCTRL, in mdp4_dsi_encoder_mode_set()
79 mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VSTART, display_v_start); in mdp4_dsi_encoder_mode_set()
80 mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VEND, display_v_end); in mdp4_dsi_encoder_mode_set()
82 mdp4_write(mdp4_kms, REG_MDP4_DSI_CTRL_POLARITY, ctrl_pol); in mdp4_dsi_encoder_mode_set()
83 mdp4_write(mdp4_kms, REG_MDP4_DSI_UNDERFLOW_CLR, in mdp4_dsi_encoder_mode_set()
86 mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_HCTL, in mdp4_dsi_encoder_mode_set()
89 mdp4_write(mdp4_kms, REG_MDP4_DSI_HSYNC_SKEW, dsi_hsync_skew); in mdp4_dsi_encoder_mode_set()
[all …]
Dmdp4_dtv_encoder.c74 mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_CTRL, in mdp4_dtv_encoder_mode_set()
77 mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_PERIOD, vsync_period); in mdp4_dtv_encoder_mode_set()
78 mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_LEN, vsync_len); in mdp4_dtv_encoder_mode_set()
79 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_HCTRL, in mdp4_dtv_encoder_mode_set()
82 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VSTART, display_v_start); in mdp4_dtv_encoder_mode_set()
83 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VEND, display_v_end); in mdp4_dtv_encoder_mode_set()
84 mdp4_write(mdp4_kms, REG_MDP4_DTV_BORDER_CLR, 0); in mdp4_dtv_encoder_mode_set()
85 mdp4_write(mdp4_kms, REG_MDP4_DTV_UNDERFLOW_CLR, in mdp4_dtv_encoder_mode_set()
88 mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_SKEW, dtv_hsync_skew); in mdp4_dtv_encoder_mode_set()
89 mdp4_write(mdp4_kms, REG_MDP4_DTV_CTRL_POLARITY, ctrl_pol); in mdp4_dtv_encoder_mode_set()
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Dmdp4_crtc.c94 mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush); in crtc_flush()
174 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg); in setup_mixer()
185 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0); in blend_setup()
186 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0); in blend_setup()
187 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0); in blend_setup()
188 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0); in blend_setup()
212 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff); in blend_setup()
213 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00); in blend_setup()
214 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op); in blend_setup()
215 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1); in blend_setup()
[all …]
Dmdp4_plane.c163 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_A(pipe), in mdp4_plane_set_scanout()
167 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_B(pipe), in mdp4_plane_set_scanout()
171 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP0_BASE(pipe), in mdp4_plane_set_scanout()
173 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP1_BASE(pipe), in mdp4_plane_set_scanout()
175 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP2_BASE(pipe), in mdp4_plane_set_scanout()
177 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP3_BASE(pipe), in mdp4_plane_set_scanout()
187 mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_MV(pipe, i), in mdp4_write_csc_config()
192 mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_PRE_BV(pipe, i), in mdp4_write_csc_config()
195 mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_POST_BV(pipe, i), in mdp4_write_csc_config()
200 mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_PRE_LV(pipe, i), in mdp4_write_csc_config()
[all …]
Dmdp4_kms.c26 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff); in mdp4_hw_init()
27 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f); in mdp4_hw_init()
30 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3); in mdp4_hw_init()
33 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222); in mdp4_hw_init()
47 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg); in mdp4_hw_init()
48 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg); in mdp4_hw_init()
50 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg); in mdp4_hw_init()
51 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg); in mdp4_hw_init()
52 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg); in mdp4_hw_init()
53 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg); in mdp4_hw_init()
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Dmdp4_irq.c16 mdp4_write(to_mdp4_kms(mdp_kms), REG_MDP4_INTR_CLEAR, in mdp4_set_irqmask()
18 mdp4_write(to_mdp4_kms(mdp_kms), REG_MDP4_INTR_ENABLE, irqmask); in mdp4_set_irqmask()
39 mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, 0xffffffff); in mdp4_irq_preinstall()
40 mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000); in mdp4_irq_preinstall()
63 mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000); in mdp4_irq_uninstall()
78 mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, status); in mdp4_irq()
Dmdp4_lvds_pll.c69 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_PHY_RESET, 0x33); in mpd4_lvds_pll_enable()
72 mdp4_write(mdp4_kms, pll_rate->conf[i].reg, pll_rate->conf[i].val); in mpd4_lvds_pll_enable()
74 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x01); in mpd4_lvds_pll_enable()
90 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, 0x0); in mpd4_lvds_pll_disable()
91 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x0); in mpd4_lvds_pll_disable()
Dmdp4_kms.h45 static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data) in mdp4_write() function