94 	mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush);  in crtc_flush()
174 	mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg);  in setup_mixer()
185 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0);  in blend_setup()
186 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0);  in blend_setup()
187 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0);  in blend_setup()
188 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0);  in blend_setup()
212 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff);  in blend_setup()
213 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00);  in blend_setup()
214 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op);  in blend_setup()
215 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1);  in blend_setup()
216 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0);  in blend_setup()
217 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0);  in blend_setup()
218 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0);  in blend_setup()
219 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0);  in blend_setup()
241 	mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma),  in mdp4_crtc_mode_set_nofb()
246 	mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0);  in mdp4_crtc_mode_set_nofb()
247 	mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma), 0);  in mdp4_crtc_mode_set_nofb()
248 	mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma),  in mdp4_crtc_mode_set_nofb()
252 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0);  in mdp4_crtc_mode_set_nofb()
253 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp),  in mdp4_crtc_mode_set_nofb()
256 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp), 0);  in mdp4_crtc_mode_set_nofb()
258 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1);  in mdp4_crtc_mode_set_nofb()
261 		mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000);  in mdp4_crtc_mode_set_nofb()
262 		mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000);  in mdp4_crtc_mode_set_nofb()
263 		mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000);  in mdp4_crtc_mode_set_nofb()
375 			mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma),  in update_cursor()
378 			mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova);  in update_cursor()
379 			mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),  in update_cursor()
384 			mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma),  in update_cursor()
396 	mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma),  in update_cursor()
562 	mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config);  in mdp4_crtc_set_config()
603 	mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel);  in mdp4_crtc_set_intf()